Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 83

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

68
INT/TRAP Control Register (ITC: 34H)
UM005003-0703
Bit
Bit/Field
R/W
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position
7
6
2
–
Z8018x
Family MPU User Manual
0
Bit/Field
TRAP
UFO
ITE2
TRAP
R/W
–
7
0
Interrupt Enable Flag 1,2 (IEF1, IEF2)
IEF1 controls the overall enabling and disabling of all internal and
external maskable interrupts (that is, all interrupts except NMI and TRAP.
0
R/W
R/W
R
R/W
UFO
R
6
0
Value Description
5
This bit is set to 1 when an undefined Op Code is fetched.
TRAP can be reset under program control by writing it
with 0, however, it cannot be written with 1 under
program control.
Undefined Fetch Object (bit 6).
When a TRAP interrupt occurs the contents of UFO allow
determination of the starting address of the undefined
instruction. This action is necessary since the TRAP may
occur on either the second or third byte of the Op Code.
UFO allows the stacked PC value to be correctly adjusted.
If UFO = 0, the first Op Code should be interpreted as the
stacked PC-1. If UFO = 1, the first Op Code address is
stacked PC-2.
Interrupt Enable — ITE2, ITE1 and ITE0 enable and
disable the external interrupt inputs INT2, INT1 and
INT0, respectively. If reset to 0, the interrupt is masked.
N/A
4
0
?
3
ITE2
R/W
2
0
ITE1
R/W
1
0
ITE0
R/W
0
1