Z8018010PSG Zilog, Z8018010PSG Datasheet - Page 84

• Manufacturer Part Number: Z8018010PSG
• Description: IC 10MHZ Z180 CMOS ENH MPU 64DIP
• Manufacturer: Zilog

Specifications of Z8018010PSG

• Processor Type: Z180
• Features: 8-Bit, Enhanced Z80 Megacell
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 64-DIP (0.750", 19.05mm)
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Core Size: 8bit
• Cpu Speed: 10MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 64
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 8018010
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3889; Z8018010PSG

If IEF1 is
the DI (Disable Interrupts) instruction and set to
Interrupts) instruction.
The purpose of IEF2 is to correctly manage the occurrence of NMI.
During NMI, the prior interrupt reception state is saved and all maskable
interrupts are automatically disabled (IEF1 copied to IEF2 and then IEF1
cleared to
the RETN (Return from Non-maskable Interrupt) automatically restores
the interrupt receiving state (by copying IEF2 to IEF1) prior to the
occurrence of NMI.
Table 8 describes how the IEF2 state can be reflected in the P/V bit of the
CPU Status Register by executing LD A, I or LD A, R instructions.
Table 8.
CPU
Operation
RESET
NMI
RETN
Interrupt except
NMI end TRAP
RETI
TRAP
EI
0
0
State of IEF1 and IEF2
, all maskable interrupts are disabled. IEF1 can be reset to
). At the end of the NMI interrupt service routine, execution of
IEF1
0
0
IEF2
0
not affected not affected
not affected not affected
1
IEF2
0
IEF1
not affected Returns from the NMI service
0
1
Family MPU User Manual
REMARKS
Inhibits the interrupt except NMI
and TRAP.
Copies the contents of IEF1 to
IEF2
routine.
Inhibits the interrupt except NMI
end TRAP
1
by the El (Enable
UM005003-0703
Z8018x
0
by
69