MC68EC020AA25 Freescale Semiconductor, MC68EC020AA25 Datasheet - Page 131

• Manufacturer Part Number: MC68EC020AA25
• Description: IC MPU 32BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020AA25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

execution of instructions. The processor also saves the contents of some of its internal
registers. The information saved on the stack is sufficient to identify the cause of the bus
fault and recover from the error.
For efficiency, the MC68020/EC020 uses two different bus error stack frame formats.
When the bus error exception is taken at an instruction boundary, less information is
required to recover from the error, and the processor builds the short bus fault stack frame
as shown in Table 6-5. When the exception is taken during the execution of an instruction,
the processor must save its entire state for recovery and uses the long bus fault stack
frame shown in Table 6-5. The format code in the stack frame distinguishes the two stack
frame formats. Stack frame formats are described in detail in 6.4 Exception Stack Frame
Formats.
If a bus error occurs during the exception processing for a bus error, address error, or
reset or while the processor is loading internal state information from the stack during the
execution of an RTE instruction, a double bus fault occurs and the processor enters the
halted state. In this case, the processor does not attempt to alter the current state of
memory. Only an external RESET can restart a processor halted by a double bus fault.
6.1.3 Address Error Exception
An address error exception occurs when the processor attempts to prefetch an instruction
from an odd address. This exception is similar to a bus error exception but is internally
initiated. A bus cycle is not executed, and the processor begins exception processing
immediately. After exception processing commences, the sequence is the same as that
for bus error exceptions described in the preceding paragraphs, except that the vector
number is 3 and the vector offset in the stack frame refers to the address error vector.
Either a short or long bus fault stack frame may be generated. If an address error occurs
during the exception processing for a bus error, address error, or reset, a double bus fault
occurs.
6.1.4 Instruction Trap Exception
Certain instructions are used to explicitly cause trap exceptions. The TRAP instruction
always forces an exception and is useful for implementing system calls in user programs.
The TRAPcc, TRAPV, cpTRAPcc, CHK, and CHK2 instructions force exceptions if the
user program detects an error, which may be an arithmetic overflow or a subscript value
that is out of bounds.
The DIVS and DIVU instructions force exceptions if a division operation is attempted with
a divisor of zero.
When a trap exception occurs, the processor copies the SR internally, enters the
supervisor privilege level (by setting the S-bit in the SR), and clears the T1 and T0 bits in
the SR. If tracing is enabled for the instruction that caused the trap, a trace exception is
taken after the RTE instruction from the trap handler is executed, and the trace
corresponds to the trap instruction; the trap handler routine is not traced. The processor
generates a vector number according to the instruction being executed; for the TRAP
6-6
M68020 USER’S MANUAL
MOTOROLA