MC68EC020AA25 Freescale Semiconductor, MC68EC020AA25 Datasheet - Page 148

• Manufacturer Part Number: MC68EC020AA25
• Description: IC MPU 32BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020AA25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

FC—Fault on Stage C
FB—Fault on Stage B
RC—Rerun Flag for Stage C
RB—Rerun Flag for Stage B
MOTOROLA
When the FC bit is set, the processor attempted to use stage C and found it to be
marked invalid due to a bus error on the prefetch for that stage. FC can be used by a
bus error handler to determine the cause(s) of a bus error exception.
When the FB bit is set, the processor attempted to use stage B and found it to be
marked invalid due to a bus error on the prefetch for that stage. FB can be used by a
bus error handler to determine the cause(s) of a bus error exception.
The RC bit is set to indicate that a fault occurred during a prefetch for stage C. The RC
bit is always set when the FC bit is set. The RC bit indicates that the word in stage C of
the instruction pipe is invalid, and the state of the bit can be used by a handler to repair
the values in the pipe after an address error or a bus error, if necessary. If the RC bit is
set when the processor executes an RTE instruction, the processor may execute a bus
cycle to prefetch the instruction word for stage C of the pipe (if it is required). If the RC
and FC bits are set, the RTE instruction automatically reruns the prefetch cycle for
stage C. The address space for the bus cycle is the program space for the privilege
level indicated in the copy of the SR on the stack. If the RC bit is clear, the words on the
stack for stage C of the pipe are accepted as valid; the processor assumes that there is
no prefetch pending for stage C and that software has repaired or filled the image of
stage C, if necessary.
The RB bit is set to indicate that a fault occurred during a prefetch for stage B. The RB
bit is always set when the FB bit is set. The RB bit indicates that the word in stage B of
the instruction pipe is invalid, and the state of the bit can be used by a handler to repair
the values in the pipe after an address error or a bus error, if necessary. If the RB bit is
set when the processor executes an RTE instruction, the processor may execute a bus
cycle to prefetch the instruction word for stage B of the pipe (if it is required). If the RB
and FB bits are set, the RTE instruction automatically reruns the prefetch cycle for stage
B. The address space for the bus cycle is the program space for the privilege level
indicated in the copy of the SR on the stack. If the RB bit is clear, the words on the
1 = Rerun faulted bus cycle or run pending prefetch
0 = Do not rerun bus cycle
15
FC
14
FB
RC
13
12
RB
Figure 6-8. Special Status Word Format
11
0
10
0
M68020 USER’S MANUAL
9
0
DF
8
RM
7
RW
6
5
SIZE
4
3
0
2
FC2–FC0
0
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