MC68EC020AA25 Freescale Semiconductor, MC68EC020AA25 Datasheet - Page 179

• Manufacturer Part Number: MC68EC020AA25
• Description: IC MPU 32BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020AA25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

When the MC68020/EC020 receives one of the three take exception coprocessor
response primitives, it acknowledges the primitive by setting the exception acknowledge
bit (XA) in the control CIR. The MC68020/EC020 sets the abort bit (AB) in the control CIR
to abort any coprocessor instruction in progress. (The 14 most significant bits of both
masks are undefined.) The MC68020/EC020 aborts a coprocessor instruction when it
detects one of the following exception conditions:
7.3.3 Save CIR
The coprocessor uses the 16-bit save CIR to communicate status and state frame format
information to the main processor while executing a cpSAVE instruction. The main
processor reads the save CIR to initiate execution of the cpSAVE instruction by the
coprocessor. The offset from the base address of the CIR set for the save CIR is $04.
Refer to 7.2.3.2 Coprocessor Format Words for more information on the save CIR.
7.3.4 Restore CIR
The main processor initiates the cpRESTORE instruction by writing a coprocessor format
word to the 16-bit restore register. During the execution of the cpRESTORE instruction,
the coprocessor communicates status and state frame format information to the main
processor through the restore CIR. The offset from the base address of the CIR set for the
restore CIR is $06. Refer to 7.2.3.2 Coprocessor Format Words for more information on
the restore CIR.
7.3.5 Operation Word CIR
The main processor writes the F-line operation word of the instruction in progress to the
16-bit operation word CIR in response to a transfer operation word coprocessor response
primitive (refer to 7.4.6 Transfer Operation Word Primitive). The offset from the base
address of the CIR set for the operation word CIR is $08.
7.3.6 Command CIR
The main processor initiates a coprocessor general category instruction by writing the
instruction command word, which follows the instruction F-line operation word in the
instruction stream, to the 16-bit command CIR. The offset from the base address of the
CIR set for the command CIR is $0A.
7-26
• An F-line emulator exception condition after reading a response primitive
• A privilege violation exception as it performs a supervisor check in response to a
• A format error exception when it receives an invalid format word or a valid format
supervisor check primitive
word that contains an invalid length
15
Figure 7-19. Control CIR Format
(UNDEFINED, RESERVED)
M68020 USER’S MANUAL
2
XA
1
AB
MOTOROLA
0