MC68EC020AA25 Freescale Semiconductor, MC68EC020AA25 Datasheet - Page 34

• Manufacturer Part Number: MC68EC020AA25
• Description: IC MPU 32BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020AA25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

2.3 EXCEPTION PROCESSING
An exception is defined as a special condition that preempts normal processing. Both
internal and external conditions can cause exceptions. External conditions that cause
exceptions are interrupts from external devices, bus errors, coprocessor-detected errors,
and reset. Instructions, address errors, tracing, and breakpoints are internal conditions
that cause exceptions. The TRAP, TRAPcc, TRAPV, cpTRAPcc, CHK, CHK2, RTE,
BKPT, CALLM, RTM, cp RESTORE, DIVS and DIVU instructions can generate exceptions
as part of their normal execution. In addition, illegal instructions, privilege violations, and
coprocessor protocol violations cause exceptions.
Exception processing, which is the transition from the normal processing of a program to
the processing required for the exception condition, involves the exception vector table
and an exception stack frame. The following paragraphs describe the exception vectors
and a generalized exception stack frame. Exception processing is discussed in detail in
Section 6 Exception Processing. Coprocessor-detected exceptions are discussed in
detail in Section 7 Coprocessor Interface Description.
2.3.1 Exception Vectors
The VBR contains the base address of the 1024-byte exception vector table, which
consists of 256 exception vectors. Exception vectors contain the memory addresses of
routines that begin execution at the completion of exception processing. These routines
perform a series of operations appropriate for the corresponding exceptions. Because the
exception vectors contain memory addresses, each consists of one long word, except for
the reset vector. The reset vector consists of two long words: the address used to initialize
the ISP and the address used to initialize the PC.
The address of an exception vector is derived from an 8-bit vector number and the VBR.
The vector numbers for some exceptions are obtained from an external device; others are
supplied automatically by the processor. The processor multiplies the vector number by
four to calculate the vector offset, which it adds to the VBR. The sum is the memory
address of the vector. All exception vectors are located in supervisor data space, except
the reset vector, which is located in supervisor program space. Only the initial reset vector
is fixed in the processor's memory map; once initialization is complete, there are no fixed
assignments. Since the VBR provides the base address of the vector table, the vector
table can be located anywhere in memory; it can even be dynamically relocated for each
task that is executed by an operating system. Details of exception processing are provided
in Section 6 Exception Processing, and Table 6-1 lists the exception vector
assignments.
MOTOROLA
M68020 USER’S MANUAL
2- 5