MC68EC020AA25 Freescale Semiconductor, MC68EC020AA25 Datasheet - Page 225

• Manufacturer Part Number: MC68EC020AA25
• Description: IC MPU 32BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020AA25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

The MOVE instruction timing tables include all necessary timing for extension word fetch,
address calculation, and operand fetch.
The instruction timing tables are used to calculate a best-case and worst-case bounds for
some target instruction stream. Calculating exact timing from the timing tables is
impossible because the tables cannot anticipate how the combination of factors will
influence every particular sequence of instructions. This is illustrated by comparing the
observed instruction timing from the prior four examples with instruction timing derived
from the instruction timing tables.
Table 8-2 lists the original instruction stream and the corresponding clock timing from the
appropriate timing tables for the best case, cache-only case, and worst case.
Table 8-3 summarizes the observed instruction timings for the same instruction stream as
executed according to the assumptions of the four examples. For each example, Table 8-
3 shows which entry (BC/CC/WC) from the timing tables corresponds to the observed
timing for each of the four instructions. Some of the observed instruction timings cannot be
found in the timing tables and appear in Table 8-3 within parentheses in the most
appropriate column. These timings occur when instruction execution overlap dynamically
alters what would otherwise be a BC, CC, or WC timing.
MOTOROLA
#1) MOVE.L
#2) ADD.L
#3) MOVE.L
#4) ADD.L
Total
Instruction
This CC time is a maximum since the times given for the
MULU.L and DIVS.L are maximums.
#1) MOVE.L
#2) ADD.L
#3) MOVE.L
#4) ADD.L
Total
D4,(A1)+
D4,D5
(A1),–(A2)
D5,D6
Table 8-2. Instruction Timings from Timing Tables
Instruction
Table 8-3. Observed Instruction Timings
BC
(1)
0
D4,(A1)+
D4,D5
(A1),–(A2)
D5,D6
Example 1
(16)
CC
M68020 USER’S MANUAL
WC
6
9
NOTE
Best Case
BC
4
6
Example 2
10
4
0
6
0
(16)
CC
WC
Cache Case
3
3
15
4
2
7
2
BC
(1)
0
Example 3
(12)
CC
4
7
Worst Case
21
6
3
9
3
WC
BC
0
0
Example 4
(13)
CC
(5)
(8)
WC
8- 11