MC68EC020AA25 Freescale Semiconductor, MC68EC020AA25 Datasheet - Page 190

• Manufacturer Part Number: MC68EC020AA25
• Description: IC MPU 32BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020AA25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

The valid EA field of the primitive format specifies the valid effective address categories
for this primitive. If the effective address specified in the instruction operation word is not a
member of the class specified by the valid EA field, the main processor aborts the
coprocessor instruction by writing an abort mask to the control CIR (refer to 7.3.2 Control
CIR) and by initiating F-line emulation exception processing. Table 7-4 lists the valid
effective address field encodings.
Even when the valid EA fields specified in the primitive and in the instruction operation
word match, the MC68020/EC020 initiates protocol violation exception processing if the
primitive requests a write to an unalterable effective address.
The length in bytes of the operand to be transferred is specified by the length field of the
primitive format. Several restrictions apply to operand lengths for certain effective
addressing modes. If the effective address is a main processor register (register direct
mode), only operand lengths of one, two, or four bytes are valid; all other lengths cause
the main processor to initiate protocol violation exception processing. Operand lengths of
0–255 bytes are valid for the memory addressing modes.
The length of 0–255 bytes does not apply to an immediate operand. The length of an
immediate operand must be one byte or an even number of bytes (less than 256), and the
direction of transfer must be to the coprocessor; otherwise, the main processor initiates
protocol violation exception processing.
When the main processor receives the evaluate effective address and transfer data
primitive during the execution of a general category instruction, it verifies that the effective
address encoded in the instruction operation word is in the category specified by the
primitive. If so, the processor calculates the effective address using the appropriate
effective address extension words at the current scanPC address and increments the
scanPC by two for each word referenced. Using long-word transfers whenever possible,
the main processor then transfers the number of bytes specified in the primitive between
the operand CIR and the effective address. Refer to 7.3.8 Operand CIR for information
concerning operand alignment for transfers involving the operand CIR.
MOTOROLA
Table 7-4. Valid Effective Address Field Codes
Field
000
001
010
011
100
101
110
111
Control Alterable
Data Alterable
Memory Alterable
Alterable
Control
Data
Memory
Any Effective Address (No Restriction)
M68020 USER’S MANUAL
Category
7- 37