MC68LC060ZU50 Freescale Semiconductor, MC68LC060ZU50 Datasheet - Page 123

• Manufacturer Part Number: MC68LC060ZU50
• Description: IC MPU 32BIT 68K 50MHZ 304-TBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060ZU50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 304-TBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

6.1.3.1 FLOATING-POINT CONDITION CODE BYTE. The FPCC byte (see Figure 6-4)
contains four condition code bits that are set at the end of all arithmetic instructions involving
the floating-point data registers. These bits are sign of mantissa (N), zero (Z), infinity (I), and
NAN. The FMOVE FPm, < ea > , FMOVEM FPm, and FMOVE FPCR instructions do not affect
the FPCC.
To aid programmers of floating-point subroutine libraries, the MC68060 implements the four
FPCC bits in hardware instead of only implementing the four IEEE conditions. An instruction
derives the IEEE conditions when needed. For example, the programmers of a complex
arithmetic multiply subroutine usually prefer to handle special data types, such as zeros,
infinities, or NANs, separately from normal data types. The floating-point condition codes
allow users to efficiently detect and handle these special values.
6.1.3.2 QUOTIENT BYTE. The quotient byte (see Figure 6-5) provides compatibility with
the MC68881/MC68882. This byte is set at the completion of the modulo (FMOD) or IEEE
remainder (FREM) instruction, and contains the seven least significant bits of the unsigned
quotient as well as the sign of the entire quotient.
The quotient bits can be used in argument reduction for transcendentals and other functions.
For example, seven bits are more than enough to determine the quadrant of a circle in which
an operand resides. The quotient field (bits 22–16) remains set until the user clears it.
6.1.3.3 EXCEPTION STATUS BYTE. The EXC byte (see Figure 6-6) contains a bit for each
floating-point exception that can occur during the most recent arithmetic instruction or move
operation. The start of most operations clears this byte; however, operations that cannot
generate floating-point exceptions (the FMOVEM and FMOVE control register instructions)
do not clear this byte. An exception handler can use this byte to determine which floating-
point exception(s) caused a trap.
MOTOROLA
31
23
S
30
Figure 6-4. Floating-Point Condition Code (FPSR)
Figure 6-5. Floating-Point Quotient Byte (FPSR)
0
22
29
21
28
M68060 USER’S MANUAL
20
27
N
QUOTIENT
19
26
Z
18
25
I
NAN
24
17
SIGN OF QUOTIENT
SEVEN LEAST SIGNIFICANT
BITS OF QUOTIENT
NOT-A-NUMBER OR UNORDERED
INFINITY
ZERO
NEGATIVE
16
Floating-Point Unit
6-5