MC68LC060ZU50 Freescale Semiconductor, MC68LC060ZU50 Datasheet - Page 326

• Manufacturer Part Number: MC68LC060ZU50
• Description: IC MPU 32BIT 68K 50MHZ 304-TBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060ZU50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 304-TBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Applications Information
Existing MC68040 TCR writes probably write these new bits as zeroes, which would mean
that the MC68060’s default translation is identical to that of the MC68040. If these bits in the
TCR are non-zero, it is possible that somewhere in the existing MC68040 code, a TCR
access would overwrite the desired bits to zero, hence returning the MC68040 default trans-
lation to be MC68040-like. If this is not desired, accesses to the TCR must be changed to
set the appropriate bits.
11.1.2.2.2 Descriptors in Cacheable Copyback Pages Prohibited. The
MC68040
allows the use of cacheable copyback pages to store page descriptors. The reason is that
when a table search is initiated, the MC68040 examines the data cache for valid descriptors.
Although the MC68040 does not allocate table descriptors into the cache on a miss, the sys-
tem software that is used to set up the descriptors may allocate descriptors into the data
cache.
Since the MC68060 totally ignores the data cache when performing a table search, a
descriptor that resides in a cache entry that is marked valid and dirty would cause incorrect
data to be used. The system software must be modified to make the pages that contain page
and table descriptors to be noncachable or cacheable writethrough to ensure coherency to
avoid this situation.
11.1.2.2.3 Page and Descriptor Faults (Access Error Handler). The access error han-
dler is entered when a table search results in an invalid table descriptor, invalid page
descriptor, supervisor protection violation, write protection violation, or a bus error. In an
MC68040 access error handler, table-search-related causes require the use of the PTEST
instruction to determine the cause of the fault.
Given the many differences in the access error handling of the MC68060 and MC68040, it
is recommended that the entire handler be replaced. Refer to Section 8 Exception Pro-
cessing for information on recovering from an access error.
Note that on unsuccessful table searches, the processor does not allocate an invalid
address translation cache (ATC) entry; therefore, a PFLUSH is not necessary to remove the
invalid ATC entry.
When an MC68040 reports a write page fault, the stack frame contains the stacked PC of
an instruction subsequent to the one that caused the write fault. On the MC68060, the
stacked PC of the stack frame points to the instruction that caused the write page fault. This
is a consequence of not having write-back slots on the stack frame.
11.1.2.2.4 PTEST, MOVEC of MMUSR, and PLPA. The PTEST instruction is unimple-
mented and an illegal instruction exception is encountered when this instruction is
attempted. Existing MC68040 software must remove all references to the PTEST instruc-
tion. It is likely that this instruction resides in the access error handler when recovering from
a page or descriptor fault. The PTEST instruction is not emulated in the M68060SP and
must therefore be avoided.
The memory management unit status register (MMUSR) of the MC68040 is not imple-
mented in the MC68060. If a MOVEC instruction is attempted to access this register, an ille-
11-4
M68060 USER’S MANUAL
MOTOROLA