MC68LC060ZU50 Freescale Semiconductor, MC68LC060ZU50 Datasheet - Page 165

• Manufacturer Part Number: MC68LC060ZU50
• Description: IC MPU 32BIT 68K 50MHZ 304-TBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060ZU50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 304-TBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Bus Operation
Figure 7-9 illustrates the transfer of a long-word operand from an odd address requiring
more than one bus cycle. For the first transfer or bus cycle, the SIZx signals specify a byte
transfer, and the byte offset is $1. The slave device supplies the byte and acknowledges the
data transfer. When the processor starts the second cycle, the SIZx signals specify a word
transfer with a byte offset of $2. The next two bytes are transferred during this cycle. The
processor then initiates the third cycle, with the SIZx signals indicating a byte transfer. The
byte offset is now $0; the port supplies the final byte and the operation is complete. This
example is similar to the one illustrated in Figure 7-10 except that the operand is word sized
and the transfer requires only two bus cycles. Figure 7-11 illustrates a functional timing dia-
gram for a misaligned long-word read transfer.
7-10
31
31
31
31
31
31
OP3
OP3
XXX
OP3
XXX
OP3
OP0
X
—
X
—
Figure 7-9. Example of a Misaligned Long-Word Transfer
Figure 7-10. Example of Misaligned Word Transfer
24 23
24 23
24 23
24 23
24 23
24 23
OP0
OP0
XXX
XXX
XXX
OP1
—
—
X
X
—
MOVE.W D0,$XXXXXXX3
MOVE.L D0,$XXXXXXX1
M68060 USER’S MANUAL
DATA BUS
DATA BUS
REGISTER
MEMORY
MEMORY
Register
16 15
16 15
16 15
16 15
16 15
16 15
OP1
XXX
OP1
XXX
XXX
OP2
OP2
—
X
—
X
8 7
8 7
8 7
8 7
8 7
8 7
OP2
XXX
XXX
OP2
OP2
OP2
OP3
OP3
—
X
X
0
0
0
0
0
0
TRANSFER 1
TRANSFER 2
TRANSFER 1
TRANSFER 2
TRANSFER 3
MOTOROLA