MC68LC060ZU50 Freescale Semiconductor, MC68LC060ZU50 Datasheet - Page 308

• Manufacturer Part Number: MC68LC060ZU50
• Description: IC MPU 32BIT 68K 50MHZ 304-TBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060ZU50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 304-TBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Instruction Execution Timing
10.3 CACHE AND ATC PERFORMANCE DEGRADATION TIMES
This section defines degradation times to MC68060 processor performance for cache and
ATC miss conditions (as detailed in 10.2 Timing Assumptions , the performance numbers
in 10.1.5 Dispatch Test 5: No Register Conflicts on sOEP.AGU Resources and 10.1.6
Dispatch Test 6: No Register Conflicts on sOEP.IEE Resources assume internal cache
hits for all memory accesses). If a cache miss is encountered, the appropriate delay times
defined in this section are to be used with the instruction times defined in 10.1.5 Dispatch
Test 5: No Register Conflicts on sOEP.AGU Resources and 10.1.6 Dispatch Test 6: No
Register Conflicts on sOEP.IEE Resources to determine MC68060 execution time.
10.3.1 Instruction ATC Miss
Assumptions:
Instruction ATC Miss = 10+3*w(3/0), if U-bit of descriptor is already set.
Instruction ATC Miss = 18+5*w(4/1), if U-bit of descriptor must be set by the MC68060.
10-12
7. Certain instructions have a variable execution time based on input operands, cache
• A single, “C-index” level, normal table search (the only U-bit update possible is for the
• Given a memory response time of “w-x-y-z” to the bus interface of the MC68060.
page descriptor itself).
state, etc. For these instructions, the execution time listed represents the maximum
value. These times are listed as: <= k(r/w) where k is the maximum time.
The following instructions perform this pipeline synchronization:
andi_to_sr
bkpt
cas
cinv
cpush
eori_to_sr
halt
lpstop
move_to_sr
movec
nop
ori_to_sr
pflush
plpa
reset
rte
stop
tas
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