MC68LC060ZU50 Freescale Semiconductor, MC68LC060ZU50 Datasheet - Page 254

• Manufacturer Part Number: MC68LC060ZU50
• Description: IC MPU 32BIT 68K 50MHZ 304-TBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060ZU50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 304-TBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Exception Processing
I/O devices or peripherals that use multiple pages (paged MMU) to define the cache mode
and that cannot tolerate duplicate reads must not allow code that causes misaligned reads
that cross page boundaries. In this case, either use the TTRs or the default TTR to define
the I/O or peripheral cache mode. I/O devices or peripherals must not be accessed using
instructions which perform both read and write cycles (e.g., a memory-to-memory move)
unless the devices accessed are capable of handling rerun cycles caused by a processor
with a restart recovery model.
8.4.4.2 Fault Address. The fault address field contains the logical address of the access
that incurred the access error. The SIZE, TT, TM, R- and W-bits of the FSLW qualify the fault
address. For MMU-related exceptions (e.g., missing page faults, write protect, supervisor
protect), the fault address is the logical address calculated by the integer unit. For mis-
aligned operand access faults, the fault address points to the initial logical address calcu-
lated by the integer unit regardless of which bus cycle actually faulted. For instruction
extension word faults, this field points to the logical address of the instruction opword and
not the extension word.
8.4.4.3 Fault Status Long Word (FSLW) . The FSLW information indicates whether an
access to the instruction stream or the data stream (or both) caused the fault and contains
status information for the faulted access. Figure 8-6 illustrates the FSLW format.
Bits 31–28, 26, and 1—Reserved by Motorola.
IO, MA—Instruction or Operand, Misaligned Access
LK—Locked Transfer
8-22
IO,MA
0, 0 = Fault occurred on the first access of a misaligned transfer, or to the
0, 1 = Fault occurred on the second or later access of a misaligned
1, 0 = Fault occurred on an instruction opword fetch.
1, 1 = Fault occurred on a fetch of an extension word.
0 =Fault did not occur on a locked transfer.
1 =Fault occurred on a locked transfer initiated by the processor (e.g., TAS, CAS, table
31
15
IO
RESERVED
searches. Also set on locked transfers within the boundaries defined by the
MOVEC of BUSCR (LOCK bit) instruction.
PBE
14
only access of an aligned transfer.
transfer.
SBE
13
PTA
28
12
Figure 8-6. Fault Status Long-Word Format
MA RESERVED
27
PTB
11
10
26
IL
M68060 USER’S MANUAL
PF
9
LK
25
SP
24
8
RW
WP
7
23
22
TWE
6
SIZE
RE
5
21
20
WE
4
TT
TTR
3
19
BPE
18
2
RESERVED
TM
1
MOTOROLA
SEE
0
16