MC68LC060ZU50 Freescale Semiconductor, MC68LC060ZU50 Datasheet - Page 182

• Manufacturer Part Number: MC68LC060ZU50
• Description: IC MPU 32BIT 68K 50MHZ 304-TBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060ZU50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 304-TBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Clock 3 (C3)
Clock 4 (C4)
Clock 5 (C5)
MOTOROLA
states are generated, a burst-inhibited line write completes in eight clocks instead of the
five required for a burst write.
The processor drives the second long word of data on the data bus and holds the address
and transfer attribute signals constant during C3. The selected device either increments
A3 and A2 to reference the next long word, or requests the processor to increment A3 and
A2 via the CLA input.
The selected device then registers this data from the data bus and asserts TA. At the end
of C3, assuming the acknowledge termination ignore state capability is disabled, the pro-
cessor samples the level of TA; if TA is asserted, the transfer terminates.
If TA is not recognized asserted at the end of C3, the processor inserts wait states instead
of terminating the transfer. The processor continues to sample TA on successive rising
edges of BCLK until TA is recognized asserted.
This clock is identical to C3 except that the value driven on the data bus corresponds to
the third long word of data for the burst.
This clock is identical to C3 except that the value driven on the data bus corresponds to
the fourth long word of data for the burst. After the processor recognizes the last TA as-
1) INCREMENT A3–A2
2) DRIVE SIZ1–SIZ0 TO LONG
3) ASSERT TS FOR ONE BCLK
4) ASSERT SAS IMMEDIATELY IF
5) PLACE DATA ON D31–D0
1) THREE-STATE D31–D0
2) NEGATE LOCK, LOCKE IF NECESSARY
1) NEGATE TIP OR START NEXT CYCLE
ACKNOWLEDGE TERMINATION IGNORE
STATE CAPABILITY DISABLED. ELSE,
ASSERT SAS AFTER WRITE PRIMARY
IGNORE STATE COUNTER HAS EXPIRED
Figure 7-21. Line Write Burst-Inhibited Cycle Flowchart
PROCESSOR
M68060 USER’S MANUAL
CONTINUED FROM FIGURE 7-20
4 LW DONE
1) DECODE ADDRESS
2) REGISTER DATA FROM D31–D0
3) ASSERT TA FOR ONE BCLK
4) NEGATE CLA
SYSTEM
4 LW NOT DONE
Bus Operation
7-27