LUPXA255A0C200

Manufacturer Part NumberLUPXA255A0C200
DescriptionIC MICRO PROCESSOR 200MHZ 256BGA
ManufacturerIntel
LUPXA255A0C200 datasheets
 

Specifications of LUPXA255A0C200

Processor TypeXScale®Speed200MHz
Voltage3.3VMounting TypeSurface Mount
Package / Case256-BGALead Free Status / RoHS StatusLead free / RoHS Compliant
Features-Other names866868
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Intel® PXA255 Processor
Specification Update
September, 2003
Order Number:
278732-007

LUPXA255A0C200 Summary of contents

  • Page 1

    ... Intel® PXA255 Processor Specification Update September, 2003 Order Number: 278732-007 ...

  • Page 2

    ... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. ...

  • Page 3

    ... Contents Revision History............................................................................................................. 5 Preface .......................................................................................................................... 6 Affected Documents/Related Documents ................................................................ 6 Nomenclature........................................................................................................... 7 General Information ................................................................................................. 8 PXA255 Processor Markings.............................................................................. 8 Summary of Changes.................................................................................................... 9 Codes Used in Summary Table ............................................................................... 9 Errata........................................................................................................................... 13 Specification Changes................................................................................................. 22 Specification Clarifications........................................................................................... 23 Documentation Changes ............................................................................................. 24 Intel® PXA255 Processor Specification Update Contents 3 ...

  • Page 4

    ... Intel® PXA255 Processor Specification Update ...

  • Page 5

    ... Added previous document changes. Modified errata 31 Added errata 32 Added documentation change 14 (deleted old changes 1-13) Added documentation change 1 (13) Added documentation changes 9, 10, 11, 12 Added errata 31 Added documentation changes Added errata 30 Added documentation changes Initial release of the Intel® PXA255 Processor Revision History 5 ...

  • Page 6

    ... It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. We have endeavored to include all documented errata in the consolidation process; however, we make no representations or warranties concerning the completeness of the Intel® PXA255 Processor Specification Update. This document may also contain information that was not previously published. ...

  • Page 7

    ... Nomenclature Errata are design defects or errors. These may cause the Intel® PXA255 Processor (PXA255 processor) behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices unless otherwise noted ...

  • Page 8

    ... Preface General Information PXA255 Processor Markings 8 Package Designator Commercial Temp or Extended Temp GD/PXA255/A0/C/400 Processor Type Stepping (A0) Processor Speed (200/300/400) Intel® PXA255 Processor Specification Update ...

  • Page 9

    ... Summary of Changes The following tables indicates the errata, specification changes, specification clarifications, or documentation changes which apply to the PXA255 processor. Intel may fix some of the errata in a future stepping of the component and account for the other outstanding issues through documentation or specification changes as noted. This table uses the following notations: ...

  • Page 10

    ... FIFOs in an unrecoverable state.” “SET_FEATURE/CLEAR_FEATURE Request with an illegal feature 19 No Fix selector value will cause the UDC controller to respond incorrectly.” “The JTAG Controller must have the 3.6864 MHz oscillator running 19 No Fix to work.” Intel® PXA255 Processor Specification Update ERRATA ...

  • Page 11

    ... Developer’s Manual 278693 4 Developer’s Manual 278693 5 Developer’s Manual Intel® PXA255 Processor Specification Update Summary of Errata (Sheet Refer Status to Fix “DMA accesses to 8bit PCMCIA I/O space cause additional reads.” “Indeterminate results may occur in certain peripherals during a ...

  • Page 12

    ... OPR bit description in Table 12-14” 278693 “The reset bits for Table 12-13 UDC Control Function Register 28 were numbered incorrectly.” 278693 29 “Mislabeled RSP bit description in Table 12-18” 278693 30 “Replaced Table 12-13.” Intel® PXA255 Processor Specification Update Documentation Changes ...

  • Page 13

    ... Perform a read back from the same location that just written to. • Perform any transaction to a memory page marked X=C=B=0 (IO cycle). Both workarounds ensure all previous memory transactions complete before execution begins on any subsequent instructions. No Fix Status: Intel® PXA255 Processor Specification Update Errata 13 ...

  • Page 14

    ... If a load or store instruction immediately follows an Invalidate Data Translation Look-aside Buffer Problem: (DTLB) Entry command (mcr p15, 0, Rd, c8, c6, 1) and the page table entry required by the load/ store instruction is resident in the data TLB, the load/store entry will be invalidated along with the 14 Intel® PXA255 Processor Specification Update ...

  • Page 15

    ... PCMCIA, and CF hard reset is asserted, the address bus is 0x0 while the chip select pin and write enable pin is Implication: still asserted. Any data at address 0x0 could be overwritten with random data. None Workaround: No Fix Status: Intel® PXA255 Processor Specification Update Errata 15 ...

  • Page 16

    ... Some frames also contain invalid data. More than 60% of the of the frames are invalid. Implication: When the core frequency is set to 100MHz, the data is transmitted correctly. Workaround: No Fix Status: 16 Card Lexar Sandisk Viking SPI Block Intel® PXA255 Processor Specification Update DaneElec X X ...

  • Page 17

    ... Implication: While in SDS, any memory operation that may cause a precise data abort must be followed by a Workaround: Drain Write Buffer command. Load Multiple/Store Multiple that may cause precise data aborts must not be used. No Fix Status: Intel® PXA255 Processor Specification Update Errata 17 ...

  • Page 18

    ... If an overrun occurs on the AC97 Receive FIFO, and a Receive FIFO Overrun error in the PCM_In Status Register is indicated, then stop the DMA channel associated with the Receive FIFO, and issue a cold reset to the AC97 circuitry and to the AC97 unit, by setting GCR[COLD_RST] to zero. No Fix Status: 18 Intel® PXA255 Processor Specification Update ...

  • Page 19

    ... If the operation of these peripherals would be adversely affected, then these peripherals would have Workaround disabled during a frequency change. • MMC • FFUART • STUART • BTUART • IrDA • SSP • UDC • AC97 No Fix Status: Intel® PXA255 Processor Specification Update Errata 19 ...

  • Page 20

    ... Invalid AC’97 interrupt may occur when the ‘cold reset’ bit is set or cleared in the GCR. Problem: A spurious interrupt may occur during a cold reset. Implication: Disable AC’97 interrupts before doing a cold reset by setting GCR[COLD_RST]. When the cold Workaround: reset event is complete, the interrupts can be re-enabled. No Fix Status: 20 Intel® PXA255 Processor Specification Update ...

  • Page 21

    ... FIQ handler may be executed twice not a branch instruction no-op is placed at the beginning of the FIQ handler, the no-op will execute twice and no Workaround: incorrect behavior will result branch instruction is placed at the beginning of the handler, it will not be executed twice. No Fix Status: Intel® PXA255 Processor Specification Update Errata 21 ...

  • Page 22

    ... Specification Changes Specification Changes There are no specification changes at this time. 22 Intel® PXA255 Processor Specification Update ...

  • Page 23

    ... Specification Clarifications There are no specification clarifications at this time. Intel® PXA255 Processor Specification Update Specification Clarifications 23 ...

  • Page 24

    ... The SSP’s control registers and the SSSR[ROR] bits are not reset when SSCR0[SSE] is cleared. It should state: The SSP’s control registers are not reset when SSCR0[SSE] is cleared. D3. 'End/Error in FIFO' interrupt occurs at or below trigger level Intel® PXA255 Processor Developer’s Manual Affected Docs: Table 11-6 states: Issue: End/error in FIFO (read-only). ...

  • Page 25

    ... SDRAM that is smaller than the default possible to preserve the SDRAM contents this, follow this procedure: 1. The SDRAM refresh time is chosen by taking the specified refresh time, typically 64 ms, and subtracting the GPIO reset time (found in the Intel® PXA26x Processor Family Electrical, Intel® PXA255 Processor Specification Update Documentation Changes ...

  • Page 26

    ... Processor type. This bit is READ ONLY. 0 – PXA255 processor 1 – reserved Processor type. This bit is READ ONLY. 0 – reserved 1 – PXA255 processor Intel® PXA255 Processor Specification Update AC97 bit_clk I2S bit_clk I2S bit_clk AC97 bit_clk AC97 bit_clk I2S bit_clk I2S bit_clk ...

  • Page 27

    ... Affected Docs: OPR bit description labeled as follows: Issue: 0x 4060_0010 Bit Bits Name OUT packet ready (read/write 1 to clear) 0 OPR 0 = OUT packet ready. It should read as follows: 0x 4060_0010 Bit Intel® PXA255 Processor Specification Update UDCCFR Reserved Description UDCCFR Reserved Description UDCCS0 reserved ...

  • Page 28

    ... SET_INTERFACE commands with no user intervention 1 – Send NAK response to SET_CONFIGURATION and SET_INTERFACE commands until UDCCFR[AREN — 1 – Reserved – Read as unknown and must be written as zero. — 1 – Reserved – Read as unknown and must be written as zero. Intel® PXA255 Processor Specification Update ...

  • Page 29

    ... Bits Name Receive short packet (read-only) 7 RSP 0 = Short packet received and ready for reading. Intel® PXA255 Processor Specification Update UDCCFR Reserved Description Reserved – Read as unknown and must be written as zero. ACK RESPONSE ENABLE (read/write 1 to set) 0 – Send NAK response to SET_CONFIGURATION and SET_INTERFACE commands 1 – ...

  • Page 30

    ... SET_INTERFACE commands with no user intervention (B-step default) 1 – Send NAK response to SET_CONFIGURATION and SET_INTERFACE commands until UDCCFR[AREN – Reserved – Read as unknown and must be written as zero. 1 – Reserved – Read as unknown and must be written as zero. Intel® PXA255 Processor Specification Update USB Device Controller ...

  • Page 31

    ... AREN 6:2 MB1 2 ACM 1 MB1 Intel® PXA255 Processor Specification Update UDCCFR Reserved Description Reserved – Read as unknown and must be written as zero. ACK RESPONSE ENABLE (read/write 1 to set Send NAK response to SET_CONFIGURATION and SET_INTERFACE commands 1 = Send ACK response to SET_CONFIGURATION and SET_INTERFACE ...

  • Page 32

    ... Documentation Changes 32 Intel® PXA255 Processor Specification Update ...