LUPXA255A0C200 Intel, LUPXA255A0C200 Datasheet - Page 14

• Manufacturer Part Number: LUPXA255A0C200
• Description: IC MICRO PROCESSOR 200MHZ 256BGA
• Manufacturer: Intel

Specifications of LUPXA255A0C200

• Processor Type: XScale®
• Speed: 200MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 866868

Errata
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Unindexed Mode LDC/STC Instructions Can Corrupt Protected Registers
Unindexed mode LDC or unindexed mode STC can corrupt protected registers.
This error can be seen in any of the following scenarios:
Do not use unindexed addressing for LDC or STC instructions
No Fix
Aborted Store That Hits the Data Cache Marks Write-back Data Dirty
An aborted store that hits in the data cache does not modify the contents of the data cache but the
dirty bit for that cache line is set.
If there is no other external bus master in the system that will be sharing memory regions with the
processor, this erratum will simply write-back data out to external memory, even though the data
really was not modified. In normal operation this will be nothing more than an extra store on the
bus that writes the same data to memory that is already there.
If another bus master in the system exists, this erratum manifests itself in the following manner.
The processor loads in a cache line from a memory region shared with another bus master. The
external bus master modifies the same line in external shared memory. The processor attempts to
modify data in the cache line, hits the cache, aborts because of MMU permissions, the data is not
modified, but sends the dirty bit. When the cache line is evicted, the original data overwrites any
data written by the external bus master.
Use one of the following suggestions:
No Fix
MAC Instructions May Not Be Executed During Debug Mode
MAC instructions may not be executed during debug mode. When the processor goes into the
debug handler and enters a special debug state, MAC instructions are not executed if another
exception occurs. The debug handler does not have any indication that the MAC instruction did not
execute.
The accumulator does not update properly or have the correct value because the MAC instruction
does not execute.
Disable debug in the Debug Control and Status Register (DCSR) before doing a MAC instruction.
No Fix
A Load That Follows a DTLB Invalidate Entry Command Will Also Be Invali-
dated.
If a load or store instruction immediately follows an Invalidate Data Translation Look-aside Buffer
(DTLB) Entry command (mcr p15, 0, Rd, c8, c6, 1) and the page table entry required by the load/
store instruction is resident in the data TLB, the load/store entry will be invalidated along with the
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During the execution of an LDC instruction, FIQ mode registers r8-r14 and debug mode
register r13 could be corrupted
During the execution of an STC instruction, Rn could be corrupted
Memory locations could be corrupted based on the base register
Mark shared memory as write-through
Use semaphores
Use other handshaking techniques to prevent collisions on shared memory
Intel® PXA255 Processor Specification Update