LUPXA255A0C200 Intel, LUPXA255A0C200 Datasheet - Page 15

• Manufacturer Part Number: LUPXA255A0C200
• Description: IC MICRO PROCESSOR 200MHZ 256BGA
• Manufacturer: Intel

Specifications of LUPXA255A0C200

• Processor Type: XScale®
• Speed: 200MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 866868

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Intel® PXA255 Processor Specification Update
target of the Invalidate D-TLB entry command. This can also occur if one instruction with an issue
latency of one cycle is executed after the Invalidate D-TLB entry command and before the load/
store instruction.
Follow all DTLB Invalidate Entry commands with two no-ops.
No Fix
Jtag Highz Instruction Not 1149.1 Compliant
JTAG HIGHZ instruction is not IEEE 1149.1 compliant.
The processor violates the IEEEE 1149.1 specification because it places the outputs into an
inactive state one clock after the HIGHZ instruction.
Insert an extra clock after the HIGHZ instruction to three-state the pads.
No Fix
Instruction Fetch Unit (IFU) Misses an External Abort
If a bus abort occurs on a code fetch while a Instruction Translation Look-aside Buffer (I-TLB)
lock instruction is outstanding, the IFU fails to abort. Instead, the IFU will execute the instruction
returned on the aborting transaction. This problem does not affect parity errors.
Execute the instruction Sub pc, pc #4 after every I-TLB or I-Cache lock command. The Sub pc, pc
#4 instruction is not predicted, which causes the pipeline to be flushed.
No Fix
SDRAM Auto Power Down Does Not Shut Off SDCLKs 0, 1, and 2 When
Their Respective Partitions Are Not Being Accessed
If MDREFR[APD] is set, the processor does not shut off the appropriate SDCLKs when their
respective partitions are not being accessed. This causes no functional problems.
When the core accesses any SDRAM partition, all SDCLKs (i.e., SDCLK<2:0>) come on, and all
SDCLKs stay on until the core does not need to access any of the SDRAM partitions.
None
No Fix
Memory Controller GPIO Pins Float High After Reset and Cause a Write to
Address 0x0
When a hard reset occurs, the address bus is driven to 0x0. If a hard reset is asserted during a static
chip select write cycle, the address bus is driven to 0x0 quickly but nCSx and nWE return to the de-
asserted state more slowly which means a write to address 0x0 can occur. This is evident with all
static memory devices, PCMCIA, and CF.
If a hard reset is asserted, the address bus is 0x0 while the chip select pin and write enable pin is
still asserted. Any data at address 0x0 could be overwritten with random data.
None
No Fix
Errata
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