LUPXA255A0C200 Intel, LUPXA255A0C200 Datasheet - Page 19

• Manufacturer Part Number: LUPXA255A0C200
• Description: IC MICRO PROCESSOR 200MHZ 256BGA
• Manufacturer: Intel

Specifications of LUPXA255A0C200

• Processor Type: XScale®
• Speed: 200MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 866868

23.
Problem:
Implication:
Workaround:
Status:
24.
Problem:
Implication:
Workaround:
Status:
25.
Problem:
Implication:
Workaround:
Status:
26.
Problem:
Implication:
Workaround:
Status:
Intel® PXA255 Processor Specification Update
SET_FEATURE/CLEAR_FEATURE Request with an illegal feature selector
value will cause the UDC controller to respond incorrectly.
If the USB host issues a SET/CLEAR feature request with an illegal feature selector value, the
UDC controller incorrectly responds to the request with an ACK handshake. The device should
respond with a STALL.
Violates the USB 1.1 protocol since the UDC controller responds with an ACK rather than a
STALL handshake to the USB host.
No Fix
The JTAG Controller must have the 3.6864 MHz oscillator running to work.
The 3.6864 MHz on-chip oscillator must be running, either from a 3.6864 MHz crystal source or
from a 3.6864 MHz clock source, in order for the JTAG Controller to work properly.
The JTAG Controller will not work with just a TCK clock source.
The 3.6864 MHz on-chip oscillator must be running, either from a 3.6864 MHz crystal source or
from a 3.6864 MHz clock source, in order for the JTAG Controller to work properly.
No Fix
DMA accesses to 8bit PCMCIA I/O space cause additional reads.
This erratum is the same as erratum 86 but with the following addition: If DMA is used to access
8bit PCMCIA I/O space, additional reads can be generated if the length in the descriptor is odd.
Do not use DMA to access to 8bit PCMCIA I/O space. If DMA is used, software must ensure that
the descriptor lengths are even.
No Fix
Indeterminate results may occur in certain peripherals during a Frequency
change if they are active
Indeterminate results may occur in certain peripherals while transmitting or receiving data during a
frequency change sequence.
If the operation of these peripherals would be adversely affected, then these peripherals would have
to be disabled during a frequency change.
No Fix
•
•
•
•
•
•
•
•
MMC
FFUART
STUART
BTUART
IrDA
SSP
UDC
AC97
Errata
19