LUPXA255A0C200 Intel, LUPXA255A0C200 Datasheet - Page 18

• Manufacturer Part Number: LUPXA255A0C200
• Description: IC MICRO PROCESSOR 200MHZ 256BGA
• Manufacturer: Intel

Specifications of LUPXA255A0C200

• Processor Type: XScale®
• Speed: 200MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 866868

Errata
20.
Problem:
Implication:
Workaround:
Status:
21.
Problem:
Implication:
Workaround:
Status:
22.
Problem:
Implication:
Workaround:
Status:
18
The first access to a disabled SDRAM partition will not do a refresh cycle.
The first access to a disabled SDRAM partition will not do a refresh cycle. The second and
subsequent accesses to a disabled SDRAM partition will perform a refresh cycle. The first access
will show up on the bus as a RAS/CAS cycle, but no refresh cycle will proceed it.
When generating refresh cycles by accessing a disabled SDRAM partition, perform two or more
accesses to cause one or more refresh cycles.
Do one more access to any disabled SDRAM partition than planned. For example, if performing 8
refresh cycles to SDRAM, software must do 9 accesses to a disabled SDRAM partition.
No Fix
Error occurs if memory access starts within last 32 bytes of a 64MB region
of static/PCMCIA memory.
If the processor accesses, either read or write, the last 32 bytes of a 64MB region of any static chip
select region or PCMCIA/CF chip select region, then data corruption will occur. This will effect all
six 64MB static memory regions and eight 64MB PCMCIA/CF memory regions. This does not
effect SDRAM memory regions.
This erratum will not occur if the processor’s memory access does not cross a 64MB boundary and
within the last 32 bytes of a 64MB static/PCMCIA memory region, any one of the following is
performed:
No Fix
Overrun on the Receive FIFO for the PCM channel of the AC97 unit will leave
the FIFOs in an unrecoverable state.
If a receive overrun occurs on the AC97 Two-channel composite PCM Receive FIFO, this will stop
the channel. The overrun can cause the most significant and least significant 16 bits of the FIFO
(i.e. the left channel and right channel) to be switched. If the DMA or core later empties the FIFO,
then this switching of data, and therefore invalid data, will continue to occur until the AC97 unit
and the FIFO pointers are reset.
Software should assume that any overrun condition is fatal and that, following the error, the FIFO
contents are invalid.
If software wishes to manually stop the DMA that services the AC97 Receive FIFO, then first
power off the ADC subsystem of the codec, then stop the DMA channel associated with the
Receive FIFO. If done quickly enough (8 sample times, 166us at 48kHz), this should avoid the
possibility of the Receive FIFO overflow and thus the Left/Right channel swapping.
If an overrun occurs on the AC97 Receive FIFO, and a Receive FIFO Overrun error in the PCM_In
Status Register is indicated, then stop the DMA channel associated with the Receive FIFO, and
issue a cold reset to the AC97 circuitry and to the AC97 unit, by setting GCR[COLD_RST] to zero.
No Fix
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processor only does a byte load or byte store on a byte boundary.
processor only does a half-word load or half-word store on a half-word boundary.
processor only does a word load or word store on a word boundary.
Intel® PXA255 Processor Specification Update