DS2141AQ+ Maxim Integrated Products, DS2141AQ+ Datasheet - Page 20

• Manufacturer Part Number: DS2141AQ+
• Description: IC CONTROLLER T1 5V 44-PLCC
• Manufacturer: Maxim Integrated Products

Specifications of DS2141AQ+

• Controller Type: T1 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 10mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC, 44-PLCC
• Operating Supply Voltage: 5 V
• Supply Current (max): 10 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FECR: FRAME ERROR COUNT REGISTER (27h)
The Frame Error Count Register (FECR) is a 8-bit counter that records either errors in the framing
pattern. The FECR will count individual bit errors in the ESF framing pattern (...001011...) if the device
is set into the ESF framing mode (CCR2.3 = 1) and it will count individual bit errors in the Ft framing
pattern (...101010...) in the D4 framing mode (CCR2.3 = 0). If RCR2.1=1, then the FECR will also record
individual bit errors in the Fs framing pattern (...001110...) when it is in the D4 framing mode. This
counter saturates at 255 and will not roll over. The counter is disabled during loss of sync conditions.
6.0 FDL/FS EXTRACTION AND INSERTION
The DS2141A has the ability to extract/insert data from/into the Facility Data Link (FDL) in the ESF
framing mode and from/into Fs-bit position in the D4 framing mode. Since SLC-96 utilizes the Fs-bit
position, this capability can also be used in SLC-96 applications. The operation of the receive and
transmit sections will be discussed separately.
6.1 Receive Section
In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the Receive FDL
register (RFDL). Since the RFDL is 8 bits in length, it will fill up every 2 ms (8 x 250 s). The DS2141A
will signal an external microcontroller that the buffer has filled via the SR2.4 bit. If enabled via IMR2.4,
the INT2 pin will toggle low indicating that the buffer has filled and needs to be read. The user has 2 ms
to read this data before it is lost. If the byte in the RFDL matches either of the bytes programmed into the
RFDLM1 or RFDLM2 registers, then the SR2.2 bit will be set to a 1 and the INT2 pin will toggled low if
enabled via IMR2.2. This feature allows an external microcontroller to ignore the FDL or Fs pattern until
an important event occurs.
The DS2141A also contains a 0 destuffer which is controlled via the CCR2.0 bit. In both ANSI T1.403
and TR54016, communications on the FDL follow a subset of a LAPD protocol. The LAPD protocol
states that no more than five 1's should be transmitted in a row so that the data does not resemble an
opening or closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.0, the DS2141A
will automatically look for five 1's in a row, followed by a 0. If it finds such a pattern, it will
automatically remove the 0. If the 0 destuffer sees six or more 1's in a row followed by a 0, the 0 is not
removed. The CCR2.0 bit should always be set to a 1 when the DS2141A is extracting the FDL. More on
how to use the DS2141A in FDL applications is covered in a separate Application Note.
(MSB)
FE7
SYMBOL
FE7
FE0
FE6
POSITION
FECR.7
FECR.0
FE5
MSB of the Frame Error count.
LSB of the Frame Error count.
NAME AND DESCRIPTION
FE4
20 of 39
FE3
FE2
FE1
(LSB)
FE0
DS2141A