DS2141AQ+ Maxim Integrated Products, DS2141AQ+ Datasheet - Page 22

• Manufacturer Part Number: DS2141AQ+
• Description: IC CONTROLLER T1 5V 44-PLCC
• Manufacturer: Maxim Integrated Products

Specifications of DS2141AQ+

• Controller Type: T1 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 10mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC, 44-PLCC
• Operating Supply Voltage: 5 V
• Supply Current (max): 10 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TFDL: TRANSMIT FDL REGISTER (7Eh)
The Transmit FDL Register (TFDL) contains the Facility Data Link (FDL) information that is to be
inserted on a byte basis into the outgoing T1 data stream. The LSB is transmitted first.
7.0 SIGNALING OPERATION
The robbed bit signaling bits in embedded in the T1 stream can be extracted from the receive stream and
inserted into the transmit stream by the DS2141A. There is a set of 12 registers for the receive side (RS1
to RS12) and 12 registers on the transmit side (TS1 to TS12). The signaling registers are detailed below.
The CCR1.5 bit is used to control the robbed signaling bits as they appear at RSER. If CCR1.5 is set to 0,
then the robbed signaling bits will appear at RSER in their proper position as they are received. If
CCR1.5 is set to a 1, then the robbed signaling bit positions will be forced to a 1 at RSER.
RS1 TO RS12: RECEIVE SIGNALING REGISTERS (60h to 6Bh)
(MSB)
(MSB)
TFDL7
A(16)
A(24)
B(16)
B(24)
C(16)
C(24)
D(16)
D(24)
A(8)
B(8)
C(8)
D(8)
SYMBOL
SYMBOL
TFDL7
TFDL0
D(24)
A(1)
A(15)
A(23)
D(15)
D(23)
B(15)
B(23)
C(15)
C(23)
A(7)
D(7)
B(7)
C(7)
TFDL6
POSITION
POSITION
TFDL.7
TFDL.0
RS12.7
A(14)
A(22)
B(14)
B(22)
C(14)
C(22)
D(14)
D(22)
RS1.0
A(6)
B(6)
C(6)
D(6)
TFDL5
A(13)
A(21)
D(13)
D(21)
B(13)
B(21)
C(13)
C(21)
A(5)
B(5)
C(5)
D(5)
NAME AND DESCRIPTION
MSB of the FDL code to be transmitted.
LSB of the FDL code to be transmitted.
NAME AND DESCRIPTION
Signaling Bit D in Channel 24.
Signaling Bit A in Channel 1.
TFDL4
22 of 39
A(12)
A(20)
D(12)
D(20)
B(12)
B(20)
C(12)
C(20)
A(4)
D(4)
B(4)
C(4)
TFDL3
A(11)
A(19)
D(11)
D(19)
B(11)
B(19)
C(11)
C(19)
A(3)
D(3)
B(3)
C(3)
TFDL2
A(10)
A(18)
D(10)
D(18)
B(10)
B(18)
C(10)
C(18)
A(2)
D(2)
B(2)
C(2)
TFDL1
A(17)
B(17)
C(17)
D(17)
D(9)
A(1)
A(9)
B(1)
B(9)
C(1)
C(9)
D(1)
(LSB)
RS11 (6A)
RS12 (6B)
RS10 (69)
RS1 (60)
RS2 (61)
RS3 (62)
RS4 (63)
RS5 (64)
RS6 (65)
RS7 (66)
RS8 (67)
RS9 (68)
TFDL0
(LSB)
DS2141A