DS2141AQ+ Maxim Integrated Products, DS2141AQ+ Datasheet - Page 21

• Manufacturer Part Number: DS2141AQ+
• Description: IC CONTROLLER T1 5V 44-PLCC
• Manufacturer: Maxim Integrated Products

Specifications of DS2141AQ+

• Controller Type: T1 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 10mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC, 44-PLCC
• Operating Supply Voltage: 5 V
• Supply Current (max): 10 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RFDL: RECEIVE FDL REGISTER (28h)
The Receive FDL Register (RFDL) reports the incoming Facility Data Link (FDL) or the incoming Fs-
bits. The LSB is received first.
RFDLM1: RECEIVE FDL MATCH REGISTER 1 (29h)
RFDLM2: RECEIVE FDL MATCH REGISTER 2 (2Ah)
When the byte in the Receive FDL Register matches either of the two Receive FDL Match Registers
(RFDLM1/RFDLM2), RSR2.2 will be set to a 1 and the
6.2 Transmit Section
The transmit section will shift out either the FDL (in the ESF framing mode) or the Fs-bits (in the D4
framing mode) contained in the Transmit FDL register (TFDL) into the T1 data stream. When a new
value is written to the TFDL, it will be multiplexed serially (LSB first) into the proper position in the
outgoing T1 data stream. After the full 8 bits have been shifted out, the DS2141A will signal the host
microcontroller that the buffer is empty and that more data is needed by setting the SR2.3 bit to a 1. The
INT2 will also toggle low if enabled via IMR2.3. The user has 2 ms (1.5 ms in SLC-96 applications) to
update the TFDL with a new value. If the TFDL is not updated, the old value in the TFDL will be
transmitted once again.
The DS2141A also contains a 0 stuffer which is controlled via the CCR2.4 bit. In both ANSI T1.403 and
TR54016, communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol states
that no more than five 1's should be transmitted in a row so that the data does not resemble an opening or
closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.4, the DS2141A will
automatically look for five 1's in a row. If it finds such a pattern, it will automatically insert a 0 after the
five 1's. The CCR2.0 bit should always be set to a 1 when the DS2141A is inserting the FDL. More on
how to use the DS2141A in FDL applications is covered in a separate Application Note.
(MSB)
(MSB)
RFDL7
RFDL7
SYMBOL
SYMBOL
RFDL7
RFDL0
RFDL7
RFDL0
RFDL6
RFDL6
POSITION
POSITION
RFDL.7
RFDL.0
RFDL.7
RFDL.0
RFDL5
RFDL5
MSB of the Received FDL Code.
NAME AND DESCRIPTION
LSB of the Received FDL Code.
NAME AND DESCRIPTION
MSB of the FDL Match Code.
LSB of the FDL Match Code.
RFDL4
RFDL4
21 of 39
RFDL3
RFDL3
INT2
will go active if enabled via IMR2.2.
RFDL2
RFDL2
RFDL1
RFDL1
RFDL0
RFDL0
(LSB)
(LSB)
DS2141A