DS2141AQ+ Maxim Integrated Products, DS2141AQ+ Datasheet - Page 24

• Manufacturer Part Number: DS2141AQ+
• Description: IC CONTROLLER T1 5V 44-PLCC
• Manufacturer: Maxim Integrated Products

Specifications of DS2141AQ+

• Controller Type: T1 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 10mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC, 44-PLCC
• Operating Supply Voltage: 5 V
• Supply Current (max): 10 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TTR1/TTR2/TTR3: TRANSMIT TRANSPARENCY REGISTERS (39h to 3Bh)
(MSB)
Each of the bit positions in the Transmit Transparency Registers (TTR1/TTR2/TTR3) represents a DS0
channel in the outgoing frame. When these bits are set to a 1, the corresponding channel is transparent (or
clear). If a DS0 is programmed to be clear, no robbed bit signaling will be inserted nor will the channel
have bit 7 stuffing performed. However, in the D4 framing mode, bit 2 will be overwritten by a 0 when a
Yellow Alarm is transmitted.
TIR1/TIR2/TIR3: TRANSMIT IDLE REGISTERS (3Ch to 3Eh)
(MSB)
TIDR: TRANSMIT IDLE DEFINITION REGISTER (3Fh)
Each of the bit positions in the Transmit Idle Registers (TIR1/TIR2/TIR3) represents a DS0 channel in
the outgoing frame. When these bits are set to a 1, the corresponding channel will transmit the Idle Code
contained in the Transmit Idle Definition Register (TIDR). Robbed bit signaling and bit 7 stuffing will
occur over the programmed Idle Code unless the DS0 channel is made transparent by the Transmit
Transparency Registers.
(MSB)
CH16
CH24
CH16
CH24
TIDR7
CH8
CH8
SYMBOL
SYMBOL
SYMBOL
TIDR7
TIDR0
CH24
CH24
CH1
CH1
CH15
CH23
CH15
CH23
CH7
CH7
TIDR6
POSITION
POSITION
POSITION
TTR3.7
TTR1.0
TTR3.7
TTR1.0
TIDR.7
TIDR.0
CH14
CH22
CH14
CH22
CH6
CH6
TIDR5
CH13
CH21
CH13
CH21
CH5
CH5
NAME AND DESCRIPTION
Transmit Transparency Registers.
0=this DS0 channel is not transparent.
1=this DS0 channel is transparent.
NAME AND DESCRIPTION
Transmit Idle Registers.
0=do not insert the Idle Code into this DS0 channel.
1=insert the Idle Code into this channel.
NAME AND DESCRIPTION
MSB of the Idle Code.
LSB of the Idle Code.
TIDR4
24 of 39
CH12
CH20
CH12
CH20
CH4
CH4
TIDR3
CH11
CH19
CH11
CH19
CH3
CH3
TIDR2
CH10
CH18
CH10
CH18
CH2
CH2
TIDR1
CH17
CH17
CH1
CH9
CH1
CH9
(LSB)
(LSB)
TTR2 (3A)
TTR3 (3B)
TTR1 (39)
TIR1 (3C)
TIR2 (3D)
TIR3 (3E)
TIDR0
(LSB)
DS2141A