DS2141AQ+ Maxim Integrated Products, DS2141AQ+ Datasheet - Page 25

• Manufacturer Part Number: DS2141AQ+
• Description: IC CONTROLLER T1 5V 44-PLCC
• Manufacturer: Maxim Integrated Products

Specifications of DS2141AQ+

• Controller Type: T1 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 10mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC, 44-PLCC
• Operating Supply Voltage: 5 V
• Supply Current (max): 10 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.0 CLOCK BLOCKING REGISTERS
The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3) and the Transmit Channel Blocking
Registers (TCBR1/TCBR2/TCBR3) control the RCHBLK and TCHBLK pins respectively. The
RCHBLK and TCHCLK pins are user-programmable outputs that can be forced either high or low during
individual channels. These outputs can be used to block clocks to a USART or LAPD controller in
Fractional T1, E1 to T1, or ISDN-PRI applications. When the appropriate bits are set to a 1, the RCHBLK
and TCHCLK pins will be held high during the entire corresponding channel time. See the timing in
Section 13 for an example.
RCBR1/RCBR2/RCBR3:
RECEIVE CHANNEL BLOCKING REGISTERS (6Ch to 6Eh)
(MSB)
TCBR1/TCBR2/TCBR3:
TRANSMIT CHANNEL BLOCKING REGISTERS (32h to 34h)
(MSB)
10.0 ELASTIC STORES OPERATION
The DS2141A has two onboard two-frame (386 bits) elastic stores. These elastic stores have two main
purposes. First, they can be used to rate convert the T1 data stream to 2.048 Mbps (or a multiple of 2.048
Mbps) which is the E1 rate. Secondly, they can be used to absorb the differences in frequency and phase
between the T1 data stream and an asynchronous (i.e., not frequency locked) backplane clock. Both
elastic stores contain full controlled slip capability which is necessary for this second purpose. The
receive side elastic store can be enabled via CCR1.2 and the transmit side elastic store is enabled via
CCR1.7.
10.1 Receive Side
If the receive side elastic store is enabled (CCR1.2 = 1), then the user must provide either a 1.544 MHz
(CCR1.3 = 0) or 2.048 MHz (CCR1.3 = 1) clock at the SYSCLK pin. The user has the option of either
providing a frame sync at the RFSYNC pin (RCR2.3 = 1) or having the RFSYNC pin provide a pulse on
CH16
CH24
CH16
CH24
CH8
CH8
SYMBOL
SYMBOL
CH24
CH24
CH1
CH1
CH15
CH23
CH15
CH23
CH7
CH7
POSITION
POSITION
RCBR3.7
RCBR1.0
RCBR3.7
RCBR1.0
CH14
CH22
CH14
CH22
CH6
CH6
CH13
CH21
CH13
CH21
CH5
CH5
NAME AND DESCRIPTION
Receive Channel Blocking Registers.
0=force the RCHBLK pin to remain low during this channel time.
1=force the RCHBLK pin high during this channel time.
NAME AND DESCRIPTION
Transmit Channel Blocking Registers.
0=force the TCHBLK pin to remain low during this channel time.
1=force the TCHBLK pin high during this channel time.
CH12
CH20
CH12
CH20
CH4
CH4
25 of 39
CH11
CH19
CH11
CH19
CH3
CH3
CH10
CH18
CH10
CH18
CH2
CH2
CH17
CH17
CH1
CH9
CH1
CH9
(LSB)
(LSB)
RCBR2 (6D)
RCBR1 (6C)
RCBR3 (6E)
TCBR1 (32)
TCBR2 (33)
TCBR3 (34)
DS2141A