Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 18

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

Z16C35 ISCC™ User’s Manual
Interfacing the ISCC™
2.4 REGISTER ACCESS (Continued)
Address*
xxxxx
00000
00000
00001
00010
00011
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Note:
* Address in this Table is AD5-AD1 in the Multiplexed Bus with the Shift Left mode selected, AD4-AD0 in the Multiplexed Bus with the
Shift Right mode selected, and D4 -D0 of the Channel Command/Address Register in the Non-multiplexed Bus mode.
2-8
Name
BCR
CCAR
DSR
ICR
IVR
ICSR
ISR
DER
DCR
RDCRA
RDCRA
TDCRA
TDCRA
RDCRB
RDCRB
TDCRB
TDCRB
RDARA
RDARA
RDARA
RDARA
TDARA
TDARA
TDARA
TDARA
RDARB
RDARB
RDARB
RDARB
TDARB
TDARB
TDARB
TDARB
Table 2-6. DMA Address Map
Description
Bus Configuration Register
Channel Command/Address Register (Write)
DMA Status (Read)
Interrupt Control Register
Interrupt Vector Register
Interrupt Command Register (Write)
Interrupt Status Register (Read)
DMA Enable/Disable Register
DMA Control Register
Reserved Address
Reserved Address
Receive DMA Count Register, Channel A (Low Byte)
Receive DMA Count Register, Channel A (High Byte)
Transmit DMA Count Register, Channel A (Low Byte)
Transmit DMA Count Register, Channel A (High Byte)
Receive DMA Count Register, Channel B (Low Byte)
Receive DMA Count Register, Channel B (High Byte)
Transmit DMA Count Register, Channel B (Low Byte)
Transmit DMA Count Register, Channel B (High Byte)
Receive DMA Address Register, Channel A (Bits 0-7)
Receive DMA Address Register, Channel A (Bits 8-15)
Receive DMA Address Register, Channel A (Bits 16-23)
Receive DMA Address Register, Channel A (Bits 24-31)
Transmit DMA Address Register, Channel A (Bits 0-7)
Transmit DMA Address Register, Channel A (Bits 8-15)
Transmit DMA Address Register, Channel A (Bits 16-23)
Transmit DMA Address Register, Channel A (Bits 24-31)
Receive DMA Address Register, Channel B (Bits 0-7)
Receive DMA Address Register, Channel B (Bits 8-15)
Receive DMA Address Register, Channel B (Bits 16-23)
Receive DMA Address Register, Channel B (Bits 24-31)
Transmit DMA Address Register, Channel B (Bits 0-7)
Transmit DMA Address Register, Channel B (Bits 8-15)
Transmit DMA Address Register, Channel B (Bits 16-23)
Transmit DMA Address Register, Channel B (Bits 24-31)
UM011001-0601