Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 53

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

UM011001-0601
all “1s” and, if this bit is set to “0”, the initial values will be
all “0s”.
The ISCC does not automatically preset the CRC genera-
tor so this must be done in software. This is accomplished
by issuing the Reset Tx CRC generator command, which
is encoded in bits D7 and D6 of WR0. For proper results,
this command must be issued while the transmitter is en-
abled and idling. If CRC is to be used the transmit CRC
generator must be enabled by setting bit D0 of WR5 to “1”.
CRC is normally calculated on all characters between
opening and closing flags, so this bit is usually set to “1” at
initialization and never changed.
Enabling the CRC generator is not sufficient to control the
transmission of CRC. In the ISCC this function is controlled
by the Tx Underrun/EOM bit, which may be reset by the
processor and set by the ISCC.
When the transmitter underruns (both the transmit buffer
and transmit shift register are empty) the state of the Tx
Underrun EOM bit determines the action taken by the IS-
CC.
If the Tx Underrun/EOM bit is set to “1” when the underrun
occurs, the transmitter will send flags.
The Reset Tx Underrun/EOM Latch command is encoded
in bits D7 and D6 of WR0.
If this bit is reset to “0” when the underrun occurs, the
transmitter will send either the accumulated CRC followed
by flags, or an abort followed by flags, depending on the
state of the Abort/Flag on Underrun bit in the WR10, Bit 1.
A summary is shown in Table 4-10.
The ISCC™ sets the Tx Underrun/EOM Latch when the
CRC or abort is loaded into the shift register for transmis-
sion. This event can cause an interrupt, and the status of
the Tx Underrun Latch can be read in RR0. The Tx Under-
run Latch may be reset by the processor via WR0.
For correct transmission of the CRC at the end of a frame,
the Reset Tx Underrun/EOM Latch command must be is-
sued after the first character is written to the ISCC but be-
fore the transmitter underruns after the last character writ-
ten to the ISCC. The command is usually issued
/EOM Latch Bit Abort/Flag
Tx Underrun
0
0
1
Table 4-10. Underrun EOM Bit
0
1
x
Action taken by ISCC
upon transmit
underrun
Sends CRC
followedby flag
Sends abort
followed by flag
Sends flag
immediately after the first character is written to the ISCC
so that the abort or CRC is sent if an underrun occurs in-
advertently. The Abort/Flag on Underrun bit (D2) in WR10
is usually set to “1” at the same time as the Tx Under-
run/EOM bit is reset so that an abort can still be sent if the
transmitter underruns. The Abort/Flag on Underrun bit is
then set to “0” near the end of the frame to allow the correct
transmission of CRC.
In this paragraph the term “completely sent” means shifted
out of the Transmit Shift register, not shifted out of the zero
inserter, which is an additional five bit times of delay. In
SDLC mode, if the transmitter is disabled during transmis-
sion of a character, that character will be “completely sent”.
This applies to both data and flags. However, if the trans-
mitter is disabled during the transmission of CRC, 16 total
bits corresponding to the two CRC bytes will be transmit-
ted but part of the bits will be from the CRC generator and
the latter part of the bits will be from the Flag register rather
than form the CRC generator. Thus part of the CRC bytes
will not be transmitted.
There are two modem control signals associated with the
transmitter provided by the ISCC.
The /RTS pin is a simple output that carries the inverted
state of the RTS bit (D1) in WR5.
The /CTS pin is ordinarily a simple input to the CTS bit in
RR0. However, if Auto Enables mode is selected this pin
becomes and enable for the transmitter. That is, if Auto En-
ables is ON and the /CTS pin is High the transmitter is dis-
abled. If the /CTS pin is Low, the transmitter is enabled.
The initialization sequence for the transmitter in SDLC
mode is: WR4 first, to select the mode, then WR10 to mod-
ify it if necessary, WR7 to program the flag, and then WR3
and WR5 to select the various options. At this point the
other registers should be initialized as necessary. When all
of this is complete, the transmitter may be enabled by set-
ting bit D3 of WR5 to “1”. Now that the transmitter is en-
abled, the CRC generator may be initialized by issuing the
Reset Tx CRC Generator command in WR0. A summary
is shown in Table 4-11.
Table 4-11. Initializing the Transmitter in SDLC Mode
Register
WR5
WR4
WR5
WR10
WR0
WR10
WR0
WR7
Bit No
5-6
1-0
6-7
6-7
6-7
2
7
1
Z16C35ISCC™ User’s Manual
Data Communication Modes
Description
Number of bits per character
Select parity
Select CRC-CCITT
Select CRC preset value
Reset Tx CRC
Abort/flag on underrun
Tx underrun
Flag
4-19
4