Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 43

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

UM011001-0601
In character-oriented modes, a special bit pattern is used
to provide character synchronization. The ISCC offers sev-
eral options to support synchronous mode including vari-
ous sync generation and checking, CRC generation and
checking, as well as modem controls and a transmitter to
receiver synchronization function.
For a 16-bit sync character, set bit D4 of WR4 to “1” and
bit D5 of WR4 and bit D0 of WR10 to “0”. In this mode the
transmitter sends the concatenation of WR6 and WR7 as
a time fill.
Because the receiver requires that sync characters be left-
justified in the registers, while the transmitter requires
them to be right justified, only the receiver will work with a
12-bit sync character. While the receiver is in External
Sync mode, the transmitter sync length may be six or eight
bits, as selected by bit D0 of WR10.
The number of bits per transmitted character is controlled
by D6 and D5 of WR5 and the way the data is formatted
within the transmit buffer. The bits in WR5 allow the option
of five, six, seven, or eight bits per character. When five
bits per character is selected the data may be formatted
before being written to the transmit buffer to allow trans-
mission of from one to five bits per character. This format-
ting is shown in Table 4-2. In all cases the data must be
right-justified, with the unused bits being ignored except in
the case of five bits per character.
An additional bit, carrying parity information, may be auto-
matically appended to every transmitted character by set-
ting bit D0 of WR4 to “1”. This parity bit is sent in addition
to the number of bits specified in WR4 or by the data for-
mat. If this bit is set to “1”, the transmitter will send even
parity, if set to “0”, the transmitted parity will be odd.
Either of two CRC polynomials may be used in synchro-
nous modes, selected by bit D2 in WR5. If this bit is set to
Register
WR4
WR6
WR7
WR10
Table 4-5. Registers Used in
Bit No
3 (=0)
2 (=0)
4 (=0)
5 (=0)
4 (=1)
5 (=0)
4 (=1)
5 (=1)
6 (=0)
7 (=0)
Character-oriented Modes
7-0
7-0
1
Select monosync mode
(8-bit sync character)
Select bisync mode
(16-bit sync character)
Select external sync mode
(external sync signal required)
Select 1x clock mode
Description
Select sync mode
Sync character (low byte)
Sync character (high byte)
Select sync character length
“1”, the CRC-16 polynomial is used and, if this bit is set to
“0”, the CRC-CCITT polynomial is used. This bit controls
the selection for both the transmitter and receiver. The ini-
tial state of the generator and checker is controlled by bit
D7 of WR10. When this bit is set to “1”, both the generator
and checker will have an initial value of all ones, if this bit
is set to “0”, the initial values will be all zeros.
The ISCC does not automatically preset the CRC genera-
tor, so this must be done in software. This is accomplished
by issuing the Reset Tx CRC Generator command, which
is encoded in bits D7 and D6 of WR0. For proper results
this command must be issued while the transmitter is en-
abled and sending sync characters.
If CRC is to be used, the transmit CRC generator must be
enabled by setting bit D0 of WR5 to “1”. This bit may also
be used to exclude certain characters from the CRC calcu-
lation. Sync characters are automatically excluded from
the CRC calculation and any characters written as data
may also be excluded from the calculation by using bit D0
of WR5. Internally, the CRC is enabled or disabled for a
particular character at the same time as the character is
loaded from the transmit buffer to the Transmit Shift regis-
ter. Thus, to exclude a character from CRC calculation bit
D0 of WR5 should be set to “0” before the character is writ-
ten to the transmit buffer. This guarantees that the internal
disable will occur when the character moves from the buff-
er to the shift register. Once the buffer becomes empty, the
Tx CRC Enable bit may be written for the next character.
Enabling the CRC generator is not sufficient to control the
transmission of CRC. In the ISCC this function is controlled
by the Tx Underrun/EOM bit, which may be reset by the
processor and set by the ISCC. When the transmitter un-
derruns (both the transmit buffer and Transmit Shift regis-
ter are empty) the state of the Tx Underrun/EOM bit deter-
mines the action taken by the ISCC. If the Tx
Underrun/EOM bit is not set when the underrun occurs, the
transmitter will send the accumulated CRC and set the Tx
Underrun/EOM bit to indicate this. This transition may be
programmed to cause an external/status interrupt, or the
Tx Underrun/EOM is available in RR0.
The Reset Tx Underrun/EOM Latch command is encoded
in bits D7 and D6 of WR0. For correct transmission of the
CRC at the end of a block of data, this command must be
issued after the first character is written to the ISCC but be-
fore the transmitter underruns after the last character writ-
ten to the ISCC. The command is usually issued immedi-
ately after the first character is written to the ISCC so that
CRC will be sent if an underrun occurs inadvertently during
the block of data.
If the transmitter is disabled during transmission of a char-
acter, that character will be sent completely. This applies
to both data and sync characters. However, if the transmit-
ter is disabled during the transmission of CRC, the 16-bit
Z16C35ISCC™ User’s Manual
Data Communication Modes
4-9
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