Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 82

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

Z16C35ISCC™ User’s Manual
Register Descriptions
5.5 READ REGISTERS (Continued)
Bit 3 is the Data Carrier Detect status
If the DCD IE bit in WR15 is set, this bit indicates the state
of the DCD pin the last time the Enabled External/Status
bits changed. Any transition on the DCD pin while no inter-
rupt is pending latches the state of the DCD pin and gen-
erates an External/Status interrupt. Any odd number of
transitions on the DCD pin while another External/Status
interrupt is pending will also cause an External/Status in-
terrupt condition. If the DCD IE is reset, this bit merely re-
ports the current, unlatched state of the DCD pin.
Bit 2 is the TX Buffer Empty status
This bit is set to “1” when the transmit buffer is empty. It is
reset while CRC is sent in a synchronous or SDLC mode
and while the transmit buffer is full. The bit is reset when a
character is loaded into the transmit buffer. This bit is al-
ways in the set condition after a hardware or channel reset.
Bit 1 is the Zero Count status
If the Zero Count interrupt Enable bit is set in WR15, this
bit is set to one while the counter in the baud rate genera-
tor is at the count of zero. If there is no other External/Sta-
tus interrupt condition pending at the time this bit is set, an
External/Status interrupt is generated. However, if there is
another External/Status interrupt pending at this time, no
interrupt is initiated until interrupt service is complete. If the
Zero Count condition does not persist beyond the end of
the interrupt service routine, no interrupt will be generated.
This bit is not latched High, even thought the other Exter-
nal/Status latches close as a result of the Low-to-High
transition on Zero Count. The interrupt routine should
check the other External/Status conditions for changes. If
none changed, Zero Count was the source. In polled appli-
cations, check the IP bit in RR3A for a status change and
then proceed as in the interrupt service routine.
Bit 0 is Receive Character Available
This bit is set to “1” when at least one character is available
in the receive FIFO and is reset when the receive FIFO is
completely empty. A channel or hardware reset empties
the receive FIFO.
5-22
P R E L I M I N A R Y
5.5.2 Read Register 1
RR1 contains the Special Receive Condition status bits
and the residue codes for the l-field in SDLC mode. Figure
5-19 shows the bit positions for RR1.
Bit 7 is the End of Frame (SDLC) status
This bit is used only in SDLC mode and indicates that a
valid closing flag has been received and that the CRC Er-
ror bit and residue codes are valid. This bit can be reset by
issuing the Error Reset command. It is also updated by the
first character of the following frame. This bit is reset in any
mode other than SDLC.
Bit 6 is the CRC/Framing Error status
If a framing error occurs (in Asynchronous mode), this bit
is set (and not latched) for the receive character in which
the framing error occurred. Detection of a framing error
adds an additional one-half bit to the character time so that
the framing error is not interpreted as a new Start bit. In
Synchronous and SDLC modes, this bit indicates the re-
sult of comparing the CRC checker to the appropriate
check value. This bit is reset by issuing an Error Reset
command, but the bit is never latched. Therefore, it is al-
ways updated when the next character is received. When
used for CRC error status in Synchronous or SDLC
modes, this bit is usually set since most bit combinations,
except for a correctly completed message, result in a non-
zero CRC.
Read Register 0
D7
D6
D5 D4 D3 D2 D1 D0
Figure 5-19. Read Register 1
Rx Character Available
Zero Count
Tx Buffer Empty
DCD
Sync/Hunt
CTS
Tx Underrun/EOM
Break/Abort
UM011001-0601