Z16C3516VSG Zilog, Z16C3516VSG Datasheet - Page 38

• Manufacturer Part Number: Z16C3516VSG
• Description: IC 16MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3516VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4690-5; Z16C3516VSG

Z16C35ISCC™ User’s Manual
Data Communication Modes
Incoming data is routed through one of several paths de-
pending on the mode and character length. In Asynchro-
nous mode, serial data enters the 3-bit delay if the charac-
ter length of seven or eight bits is selected. If a character
length of five or six bits is selected, data enters the receive
shift register directly.
In synchronous modes, the data path is determined by the
phase of the receive process currently in operation. A syn-
chronous receive operation begins with a hunt phase in
which a bit pattern that matches the programmed sync
characters (6-,8-, or 16-bit is searched).
The incoming data then passes through the Sync register
and is compared to a sync character stored in WR6 or
WR7 (depending on which mode it is in). The Monosync
mode matches the sync character programmed in WR7
and the character assembled in the Receive Sync register
to establish synchronization.
Synchronization is achieved differently in the Bisync
mode. Incoming data is shifted to the Receive Shift register
while the next eight bits of the message are assembled in
the Receive Sync register. If these two characters match
the programmed characters in WR6 and WR7, synchroni-
zation is established. Incoming data can then bypass the
Receive Sync register and enter the 3-bit delay directly.
The SDLC mode of operation uses the receive Sync regis-
ter to monitor the receive data stream and to perform zero
4.2 ASYNCHRONOUS MODE
In asynchronous communications data is transferred in the
format shown in Figure 4-3.
The transmission of a character begins when the line
makes a transition from the “1” state, or MARK condition to
the “0” state or SPACE condition. This transition is the ref-
erence by which the character’s bit cell boundaries are de-
fined. Though the transmitter and receiver have no com-
mon clock signal, there must be an agreement as to the
4-4
1
0
Idle State
of Line
Start
Figure 4-3. Asynchronous Message Format
Bit
LSB
Data Field
deletion when necessary; i.e., when five continuous “1s”
are received, the sixth bit is inspected and deleted from the
data stream if it is “0”. The seventh bit is inspected only if
the sixth bit equals one. If the seventh bit is “0”, a flag se-
quence has been received and the receiver is synchro-
nized to that flag. If the seventh bit is a “1” an abort or an
EOP (End Of Poll) is recognized, depending upon the se-
lection of either the normal SDLC mode or SDLC Loop
mode.
The same path is taken by incoming data for both SDLC
modes. The reformatted data enters the 3-bit delay and is
transferred to the Receive Shift register. The SDLC re-
ceive operation begins in the hunt phase by attempting to
match the assembled character in the Receive Shift Reg-
ister with the flag pattern in WR7. Then the flag character
is recognized, subsequent data is routed through the same
path, regardless of character length.
Either the CRC-16 or CRC-SDLC cyclic redundancy check
(CRC) polynomial can be used for both Monosync and Bi-
sync modes, but only the CRC-SDLC polynomial is used
for SDLC operation. The data path taken for each mode is
also different. Bisync protocol is a byte-oriented operation
that requires the CPU to decide whether or not a data char-
acter is to be included in CRC calculation. An 8-bit delay in
all synchronous modes except SDLC is allowed for this
process. In SDLC mode, all bytes are included in the CRC
calculation.
data rate so that the receiver can always sample the data
in the center of the bit cell.
The character can be broken up into four fields:
1. Start bit - signals the beginning of a character frame.
Parity
Bit
Bit(s)
1
Stop
1.5
2
UM011001-0601