CY7C63903-PVXC Cypress Semiconductor Corp, CY7C63903-PVXC Datasheet - Page 2

• Manufacturer Part Number: CY7C63903-PVXC
• Description: IC USB PERIPHERAL CTRLR 28-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63903-PVXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-QSOP
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document 38-08035 Rev. *E
2.0
Cypress has reinvented its leadership position in the low-
speed USB market with a new family of innovative microcon-
trollers. Introducing enCoRe II USB — “enhanced Component
Reduction.” Cypress has leveraged its design expertise in
USB solutions to advance its family of low-speed USB micro-
controllers, which enable peripheral developers to design new
products with a minimum number of components. The
enCoRe II USB technology builds on to the enCoRe family.
The enCoRe family has an integrated oscillator that eliminates
the external crystal or resonator, reducing overall cost. Also
integrated into this chip are other external components
commonly found in low-speed USB applications such as pull-
up resistors, wake-up circuitry, and a 3.3V regulator.
All of this adds up to a lower system cost.
The enCoRe II is an 8-bit Flash-programmable microcontroller
with integrated low-speed USB interface. The instruction set
has been optimized specifically for USB and PS/2 operations,
although the microcontrollers can be used for a variety of other
embedded applications.
The enCoRe II features up to 36 general-purpose I/O (GPIO)
pins to support USB, PS/2 and other applications. The I/O pins
are grouped into five ports (Port 0 to 4). The pins on Port 0 and
Port 1 may each be configured individually while the pins on
Ports 2, 3, and 4 may only be configured as a group. Each
GPIO port supports high-impedance inputs, configurable pull-
up, open drain output, CMOS/TTL inputs, and CMOS output
with up to five pins that support programmable drive strength
of up to 50-mA sink current. GPIO Port 1 features four pins that
interface at a voltage level of 3.3 volts. Additionally, each I/O
pin can be used to generate a GPIO interrupt to the microcon-
troller. Each GPIO port has its own GPIO interrupt vector with
the exception of GPIO Port 0. GPIO Port 0 has three dedicated
pins that have independent interrupt vectors (P0.2 - P0.4).
The enCoRe II features an internal oscillator. With the
presence of USB traffic, the internal oscillator can be set to
precisely tune to USB timing requirements (24 MHz ±1.5%).
Optionally, an external 12-MHz or 24-MHz crystal can be used
to provide a higher precision reference for USB operation. The
clock generator provides the 12-MHz and 24-MHz clocks that
remain internal to the microcontroller.
The enCoRe II has up to eight Kbytes of Flash for user’s code
and up to 256 bytes of RAM for stack space and user
variables.
In addition, the enCoRe II includes a Watchdog timer, a
vectored interrupt controller, a 16-bit Free-Running Timer, and
Capture Timers. The Power-on reset circuit detects logic when
power is applied to the device, generates resets the logic to a
known state, and begins executing instructions at Flash
address 0x0000. When power falls below a programmable trip
voltage generates reset or may be configured to generate
interrupt. There is a Low-voltage detect circuit that detects
when V
configurable to generate an LVD interrupt to inform the
processor about the low-voltage event. POR and LVD share
CC
Introduction
drops below a programmable trip voltage. It may be
the same interrupt. There is no separate interrupt for each. The
Watchdog timer can be used to ensure the firmware never gets
stalled in an infinite loop.
The microcontroller supports 23 maskable interrupts in the
vectored interrupt controller. Interrupt sources include a USB
bus reset, LVR/POR, a programmable interval timer, a
1.024-ms output from the Free Running Timer, three USB
endpoints, two capture timers, five GPIO Ports, three GPIO
pins, two SPI, a 16-bit free running timer wrap, an internal
wake-up timer, and a bus active interrupt. The wake-up timer
causes periodic interrupts when enabled. The USB endpoints
interrupt after a USB transaction complete is on the bus. The
capture timers interrupt whenever a new timer value is saved
due to a selected GPIO edge event. A total of eight GPIO
interrupts support both TTL or CMOS thresholds. For
additional flexibility, on the edge sensitive GPIO pins, the
interrupt polarity is programmable to be either rising or falling.
The free-running 16-bit timer provides two interrupt sources:
the programmable interval timer with 1-µs resolution and the
1.024-ms outputs. The timer can be used to measure the
duration of an event under firmware control by reading the
timer at the start and at the end of an event, then calculating
the difference between the two values. The two 8-bit capture
timers save a programmable 8-bit range of the free-running
timer when a GPIO edge occurs on the two capture pins (P0.5,
P0.6). The two 8-bit captures can be ganged into a single
16-bit capture.
The enCoRe II includes an integrated USB serial interface
engine (SIE) that allows the chip to easily interface to a USB
host. The hardware supports one USB device address with
three endpoints.
The USB D+ and D– pins can optionally be used as PS/2
SCLK and SDATA signals so that products can be designed to
respond to either USB or PS/2 modes of operation. PS/2
operation is supported with internal 5-KΩ pull-up resistors on
P1.0 (D+) and P1.1 (D–) and an interrupt to signal the start of
PS/2 activity. In USB mode, the integrated 1.5-KΩ pull-up
resistor on D– can be controlled under firmware. No external
components are necessary for dual USB and PS/2 systems,
and no GPIO pins need to be dedicated to switching between
modes. Slow edge rates operate in both modes to reduce EMI.
The enCoRe II supports in-system programming by using the
D+ and D– pins as the serial programming mode interface.
The programming protocol is not USB.
3.0
In this document, bit positions in the registers are shaded to
indicate which members of the enCoRe II family implement the
bits.
CY7C639xx and CY7C638xx only
CY7C639xx only
Available in all enCoRe II family members
Conventions
CY7C63310
CY7C638xx
CY7C639xx
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