CY7C63903-PVXC Cypress Semiconductor Corp, CY7C63903-PVXC Datasheet - Page 32

• Manufacturer Part Number: CY7C63903-PVXC
• Description: IC USB PERIPHERAL CTRLR 28-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63903-PVXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-QSOP
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document 38-08035 Rev. *E
14.2.15 P1.0/D+ Configuration
Table 14-11. P1.0/D+ Configuration (P10CR) [0x0D] [R/W]
14.2.16 P1.1/D– Configuration
Table 14-12. P1.1/D– Configuration (P11CR) [0x0E] [R/W]
14.2.17 P1.2 Configuration
Table 14-13. P1.2 Configuration (P12CR) [0x0F] [R/W]
14.2.18 P1.3 Configuration (SSEL)
Table 14-14. P1.3 Configuration (P13CR) [0x10] [R/W]
This register controls the operation of the P1.0 (D+) pin when the USB interface is not enabled, allowing the pin to be used as
a PS2 interface or a GPIO. See Table 21-1 for information on enabling USB. When USB is enabled, none of the controls in this
register have any affect on the P1.0 pin.
Note: The P1.0 is an open drain only output. It can actively drive a signal low, but cannot actively drive a signal high.
Bit 1: PS/2 Pull-up Enable
0 = Disable the 5K-ohm pull-up resistors
1 = Enable 5K-ohm pull-up resistors for both P1.0 and P1.1. Enable the use of the P1.0 (D+) and P1.1 (D–) pins as a PS2 style
interface
This register controls the operation of the P1.1 (D–) pin when the USB interface is not enabled, allowing the pin to be used as
a PS2 interface or a GPIO. See Table 21-1 for information on enabling USB. When USB is enabled, none of the controls in this
register have any affect on the P1.1 pin. When USB is disabled, the 5-Kohm pull-up resistor on this pin can be enabled by the
PS/2 Pull-up Enable bit of the P10CR Register (Table 14-11)
Note: There is no 2-mA sourcing capability on this pin. The pin can only sink 5 mA at V
This register controls the operation of the P1.2
Bit 7: CLK Output
0 = The internally selected clock is not sent out onto P1.2 pin
1 = This CLK Output is used to observe connected external crystal oscillator clock connected in CY7C639xx. When CLK Output
is set, the internally selected clock is sent out onto P1.2 pin
This register controls the operation of the P1.3 pin. This register exists in all enCoRe II parts
The P1.3 GPIO’s threshold is always set to TTL
When the SPI hardware is enabled, the output enable and output state of the pin is controlled by the SPI circuitry. When the SPI
hardware is disabled, the pin is controlled by the Output Enable bit and the corresponding bit in the P1 data register.
Regardless of whether the pin is used as an SPI or GPIO pin the Int Enable, Int act Low, 3.3V Drive, High Sink, Open Drain, and
Pull-up Enable control the behavior of the pin
The 50-mA sink drive capability is only available in the CY7C638xx. In the CY7C639xx, only 8-mA sink drive capability is available
on this pin regardless of the setting of the High Sink bit
Read/Write
Read/Write
Read/Write
Read/Write
Default
Default
Default
Default
Field
Field
Field
Field
Bit #
Bit #
Bit #
Bit #
CLK Output
Reserved
Reserved
Reserved
R/W
R/W
7
0
7
–
0
7
0
7
–
0
Int Enable
Int Enable
Int Enable
Int Enable
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
Int Act Low
Int Act Low
Int Act Low
Int Act Low
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
TTL Threshold
3.3V Drive
R/W
R/W
4
–
0
4
–
0
4
0
4
0
Reserved
Reserved
Reserved
High Sink
R/W
3
–
0
3
–
0
3
–
0
3
0
Open Drain
Open Drain
Open Drain
OL3
R/W
R/W
R/W
2
–
0
2
0
2
0
2
0
(Section 26.0)
Pull-up Enable
Pull-up Enable
PS/2 Pull-up
Reserved
Enable
R/W
R/W
R/W
1
0
1
–
0
1
0
1
0
CY7C63310
CY7C638xx
CY7C639xx
Page 32 of 68
Output Enable
Output Enable
Output Enable
Output Enable
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0