CY7C63903-PVXC Cypress Semiconductor Corp, CY7C63903-PVXC Datasheet - Page 25

• Manufacturer Part Number: CY7C63903-PVXC
• Description: IC USB PERIPHERAL CTRLR 28-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63903-PVXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-QSOP
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document 38-08035 Rev. *E
Table 11-2. Reset Watchdog Timer (RESWDT) [0xE3] [W]
12.0
The CPU can only be put to sleep by the firmware. This is
accomplished by setting the Sleep bit in the System Status and
Control Register (CPU_SCR). This stops the CPU from
executing instructions, and the CPU will remain asleep until an
interrupt comes pending, or there is a reset event (either a
Power-on Reset, or a Watchdog Timer Reset).
The Low-voltage Detection circuit (LVD) drops into fully
functional power-reduced states, and the latency for the LVD
is increased. The actual latency can be traded against power
consumption by changing Sleep Duty Cycle field of the
ECO_TR Register.
The Internal 32-KHz Low-speed Oscillator remains running.
Prior to entering suspend mode, firmware can optionally
configure the 32-KHz Low-speed Oscillator to operate in a low-
power mode to help reduce the over all power consumption
(Using Bit 7, Table 10-3). This will help save approximately
5 µA; however, the trade off is that the 32-KHz Low-speed
Oscillator will be less accurate (–85% to +120% deviation).
All interrupts remain active. Only the occurrence of an interrupt
will wake the part from sleep. The Stop bit in the System Status
and Control Register (CPU_SCR) must be cleared for a part
to resume out of sleep. The Global Interrupt Enable bit of the
CPU Flags Register (CPU_F) does not have any effect. Any
unmasked interrupt will wake the system up. As a result, any
Any write to this register will clear Watchdog Timer, a write of 0x38 will also clear the Sleep Timer
Bit [7:0]: Reset Watchdog Timer [7:0]
Read/Write
Default
Field
Bit #
Sleep Mode
W
7
0
W
6
0
W
5
0
Reset Watchdog Timer [7:0]
W
4
0
interrupts not intended for waking should be disabled through
the Interrupt Mask Registers.
When the CPU enters sleep mode the CPUCLK Select (Bit 1,
Table 10-4) is forced to the Internal Oscillator. The internal
oscillator recovery time is three clock cycles of the Internal
32-KHz Low-power Oscillator. The Internal 24-MHz Oscillator
restarts immediately on exiting Sleep mode. If the external
crystal oscillator is used, firmware will need to switch the clock
source for the CPU.
Unlike the Internal 24-MHz Oscillator, the external oscillator is
not automatically shut down during sleep. Systems that need
the external oscillator disabled in sleep mode will need to
disable the external oscillator prior to entering sleep mode. In
systems where the CPU runs off the external oscillator,
firmware will need to switch the CPU to the internal oscillator
prior to disabling the external oscillator.
On exiting sleep mode, once the clock is stable and the delay
time has expired, the instruction immediately following the
sleep instruction is executed before the interrupt service
routine (if enabled).
The Sleep interrupt allows the microcontroller to wake up
periodically and poll system components while maintaining
very low average power consumption. The Sleep interrupt
may also be used to provide periodic interrupts during non-
sleep modes.
W
3
0
W
2
0
W
1
0
CY7C63310
CY7C638xx
CY7C639xx
Page 25 of 68
W
0
0