CY7C63903-PVXC Cypress Semiconductor Corp, CY7C63903-PVXC Datasheet - Page 29

• Manufacturer Part Number: CY7C63903-PVXC
• Description: IC USB PERIPHERAL CTRLR 28-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63903-PVXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-QSOP
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document 38-08035 Rev. *E
14.1.5
Table 14-5. P4 Data Register (P4DATA) [0x04] [R/W]
14.2
All the GPIO configuration registers have common configu-
ration controls. The following are the bit definitions of the GPIO
configuration registers
14.2.1
When set, the Int Enable bit allows the GPIO to generate inter-
rupts. Interrupt generate can occur regardless of whether the
pin is configured for input or output. All interrupts are edge
sensitive, however for any interrupt that is shared by multiple
sources (i.e., Ports 2, 3, and 4) all inputs must be deasserted
before a new interrupt can occur.
When clear, the corresponding interrupt is disabled on the pin.
It is possible to configure GPIOs as outputs, enable the
interrupt on the pin and then to generate the interrupt by
driving the appropriate pin state. This is useful in test and may
have value in applications as well.
14.2.2
When set, the corresponding interrupt is active on the falling
edge.
When clear, the corresponding interrupt is active on the rising
edge.
14.2.3
When set, the input has TTL threshold. When clear, the input
has standard CMOS threshold.
14.2.4
When set, the output can sink up to 50 mA.
When clear, the output can sink up to 8 mA.
On the CY7C639xx, only the P3.7, P2.7, P0.1, and P0.0 have
50-mA sink drive capability. Other pins have 8-mA sink drive
capability.
On the CY7C638xx, only the P1.7–P1.3 have 50-mA sink drive
capability. Other pins have 8-mA sink drive capability.
14.2.5
When set, the output on the pin is determined by the Port Data
Register. If the corresponding bit in the Port Data Register is
This register contains the data for Port 4. Writing to this register sets the bit values to be output on output-enabled pins. Reading
from this register returns the current state of the Port 2 pins
Bit [7:4]: Reserved
Bit [3:0]: P4 Data [3:0]
P4.3–P4.0 only exist in the CY7C639xx except the CY7C63903-PVXC
Read/Write
Default
Field
Bit #
P4 Data
GPIO Port Configuration
Int Enable
Int Act Low
TTL Thresh
High Sink
Open Drain
R
7
0
R
6
0
Reserved
R
5
0
R
4
0
set, the pin is in high-impedance state. If the corresponding bit
in the Port Data Register is clear, the pin is driven low.
When clear, the output is driven low or high.
14.2.6
When set the pin has a 7K pull-up to V
with V3.3 enabled).
When clear, the pull-up is disabled.
14.2.7
When set, the output driver of the pin is enabled.
When clear, the output driver of the pin is disabled.
For pins with shared functions there are some special cases.
P0.0(CLKIN) and P0.1(CLKOUT) can not be output enabled
when the crystal oscillator is enabled. Output enables for these
pins are overridden by XOSC Enable.
P1.2(VREG), P1.3(SSEL), P1.4(SCLK), P1.5(SMOSI) and
P1.6(SMISO) can be used for their dedicated functions or for
GPIO. To enable the pin for GPIO use clear the corresponding
SPI Use bit or the Output Enable will have no effect.
14.2.8
The P1.2(VREG), P1.3(SSEL), P1.4(SCLK), P1.5(SMOSI)
and P1.6(SMISO) pins can be used for their dedicated
functions or for GPIO. To enable the pin for GPIO, clear the
corresponding VREG Output or SPI Use bit. The SPI function
controls the output enable for its dedicated function pins when
their GPIO enable bit is clear. The VREG output is not
available on the CY7C63801 and CY7C63310.
14.2.9
The
P1.6(SMISO) pins have an alternate voltage source from the
voltage regulator. If the 3.3V Drive bit is set a high level is
driven from the voltage regulator instead of from V
the 3.3V Drive bit does not enable the voltage regulator. That
must be done explicitly by setting the VREG Enable bit in the
VREGCR Register (Table 19-1).
P1.3(SSEL),
Pull-up Enable
Output Enable
VREG Output / SPI Use
3.3V Drive
R/W
3
0
P1.4(SCLK),
R/W
2
0
P4.3–P4.0
R/W
CC
1
0
P1.5(SMOSI)
CY7C63310
CY7C638xx
CY7C639xx
(or VREG for ports
Page 29 of 68
CC
R/W
. Setting
0
0
and