CY7C63903-PVXC Cypress Semiconductor Corp, CY7C63903-PVXC Datasheet - Page 28

• Manufacturer Part Number: CY7C63903-PVXC
• Description: IC USB PERIPHERAL CTRLR 28-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63903-PVXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-QSOP
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document 38-08035 Rev. *E
14.1.2
Table 14-2. P1 Data Register (P1DATA) [0x01] [R/W]
14.1.3
Table 14-3. P2 Data Register (P2DATA) [0x02] [R/W]
14.1.4
Table 14-4. P3 Data Register (P3DATA) [0x03] [R/W]
This register contains the data for Port 1. Writing to this register sets the bit values to be output on output enabled pins. Reading
from this register returns the current state of the Port 1 pins.
Bit 7: P1.7 Data
P1.7 only exists in the CY7C638xx and CY7C639xx
Bit [6:3]: P1.6–P1.3 Data/SPI Pins (SMISO, SMOSI, SCLK, SSEL)
Beside their use as the P1.6–P1.3 GPIOs, these pins can also be used for the alternate function as the SPI interface pins. To
configure the P1.6–P1.3 pins, refer to the P1.3–P1.6 Configuration Register (Table 14-14)
The use of the pins as the P1.6–P1.3 GPIOs and the alternate functions exist in all the enCoRe II parts.
Bit 2: P1.2/VREG
On the CY7C639xx, this pin can be used as the P1.2 GPIO or the VREG output. If the VREG output is enabled (Bit 0
Table 19-1 is set), a 3.3V source is placed on the pin and the GPIO function of the pin is disabled
On the CY7C63813, this pin can only be used as the VREG output when USB mode is enabled. In non-USB mode, this pin can
be used as the P1.2 GPIO
The VREG output is not available in the CY7C63310 and CY7C63801
Bit [1:0]: P1.1–P1.0 / D– and D+
When USB mode is disabled (Bit 7 in Table 21-1 is clear), the P1.1 and P1.0 bits are used to control the state of the P1.0 and
P1.1 pins. When the USB mode is enabled, the P1.1 and P1.0 pins are used as the D– and D+ pins respectively. If the USB
Force State bit (Bit 0 in Table 18-1) is set, the state of the D– and D+ pins can be controlled by writing to the D– and D+ bits
This register contains the data for Port 2. Writing to this register sets the bit values to be output on output enabled pins. Reading
from this register returns the current state of the Port 2 pins
Bit [7:2]: P2 Data [7:2]
P2.7–P2.2 only exist in the CY7C639xx. Note that the CY7C63903-PVXC (28 pin SSOP package) only has P2.7–P2.4
Bit [1:0]: P2 Data [1:0]
P2.1–P2.0 only exist in the CY7C63823 and CY7C639xx (except the CY7C63903-PVXC 28 pin SSOP package)
This register contains the data for Port 3. Writing to this register sets the bit values to be output on output enabled pins. Reading
from this register returns the current state of the Port 3 pins
Bit [7:2]: P3 Data [7:2]
P3.7–P3.2 only exist in the CY7C639xx. Note that the CY7C63903-PVXC 28 pin SSOP package only has P3.7–P3.4
Bit [1:0]: P3 Data [1:0]
P3.1–P3.0 only exist in the CY7C63823 and CY7C639xx (except the CY7C63903-PVXC 28 pin SSOP package)
Read/Write
Read/Write
Read/Write
Default
Default
Default
Field
Field
Field
Bit #
Bit #
Bit #
P1 Data
P2 Data
P3 Data
P1.7
R/W
R/W
R/W
7
0
7
0
7
0
P1.6/SMISO
R/W
R/W
R/W
6
0
6
0
6
0
P1.5/SMOSI
R/W
R/W
R/W
5
0
5
0
5
0
P2.7–P2.2
P3.7–P3.2
P1.4/SCLK
R/W
R/W
R/W
4
0
4
0
4
0
P1.3/SSEL
R/W
R/W
R/W
3
0
3
0
3
0
P1.2/VREG
R/W
R/W
R/W
2
0
2
0
2
0
P1.1/D–
R/W
R/W
R/W
1
0
1
0
1
0
CY7C63310
CY7C638xx
CY7C639xx
P2.1–P2.0
P3.1–P3.0
Page 28 of 68
P1.0/D+
R/W
R/W
R/W
0
0
0
0
0
0