CY7C63903-PVXC Cypress Semiconductor Corp, CY7C63903-PVXC Datasheet - Page 34

• Manufacturer Part Number: CY7C63903-PVXC
• Description: IC USB PERIPHERAL CTRLR 28-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63903-PVXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-QSOP
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document 38-08035 Rev. *E
Table 14-18. P3 Configuration (P3CR) [0x16] [R/W] (continued)
14.2.23 P4 Configuration
Table 14-19. P4 Configuration (P4CR) [0x17] [R/W]
15.0
The SPI Master/Slave Interface core logic runs on the SPI
clock domain, making its functionality independent of system
clock speed. SPI is a four pin serial interface comprised of a
clock, an enable and two data pins.
15.1
Table 15-1. SPI Data Register (SPIDATA) [0x3C] [R/W]
When an interrupt occurs to indicate to firmware that a byte of
receive data is available, or the transmitter holding register is
empty, firmware has 7 SPI clocks to manage the buffers—to
This register exists in CY7C638xx and CY7C639xx. In CY7C638xx this register controls the operation of pins P3.0–P3.1. In the
CY7C639xx, this register controls the operation of pins P3.0–P3.7
The 50-mA sink drive capability is only available on pin P3.7 and only on the CY7C639xx. In the CY7C638xx, only 8-mA sink
drive capability is available on this pin regardless of the setting of the High Sink bit
This register exists only in the CY7C639xx. This register controls the operation of pins P4.0–P4.3
When read, this register returns the contents of the receive buffer. When written, it loads the transmit holding register
Bit [7:0]: SPI Data [7:0]
Read/Write
Read/Write
Default
Default
Field
Field
Bit #
Bit #
SPI Data Register
Serial Peripheral Interface (SPI)
Reserved
R/W
7
–
0
7
0
Int Enable
R/W
R/W
6
0
6
0
Int Act Low
R/W
R/W
5
0
5
0
TTL Thresh
R/W
R/W
4
0
4
0
SPIData[7:0]
empty the receiver buffer, or to refill the transmit holding
register. Failure to meet this timing requirement will result in
incorrect data transfer.
Reserved
R/W
3
–
0
3
0
Open Drain
R/W
R/W
2
0
2
0
Pull-up Enable
R/W-
R/W
1
0
1
0
CY7C63310
CY7C638xx
CY7C639xx
Page 34 of 68
Output Enable
R/W
R/W
0
0
0
0