CY7C63903-PVXC Cypress Semiconductor Corp, CY7C63903-PVXC Datasheet - Page 46

• Manufacturer Part Number: CY7C63903-PVXC
• Description: IC USB PERIPHERAL CTRLR 28-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63903-PVXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-QSOP
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document 38-08035 Rev. *E
17.4.3
Table 17-9. Interrupt Vector Clear Register (INT_VC) [0xE2] [R/W]
18.0
Although the USB transceiver has features to assist in inter-
facing to PS/2 these features are not controlled using these
registers. These registers only control the USB interfacing
features. PS/2 interfacing options are controlled by the D+/D–
GPIO Configuration register (See Section Table 14.2.15).
18.1
Table 18-1. USB Transceiver Configure Register (USBXCR) [0x74] [R/W]
The Interrupt Vector Clear Register (INT_VC) holds the interrupt vector for the highest priority pending interrupt when read, and
when written will clear all pending interrupts
Bit [7:0]: Pending Interrupt [7:0]
8-bit data value holds the interrupt vector for the highest priority pending interrupt. Writing to this register will clear all pending
interrupts.
Bit 7: USB Pull-up Enable
0 = Disable the pull-up resistor on D–
1 = Enable the pull-up resistor on D–. This pull-up is to V
VREG is enabled
Bit [6:1]: Reserved
Bit 0: USB Force State
This bit allows the state of the USB I/O pins D- and D+ to be forced to a state while USB is enabled
0 = Disable USB Force State
1 = Enable USB Force State. Allows the D- and D+ pins to be controlled by P1.1 and P1.0 respectively when the USBIO is in
USB mode. Refer to Section 14.2.15 for more information
Read/Write
Read/Write
Default
Default
Field
Field
Bit #
Bit #
Interrupt Vector Clear Register
USB Transceiver Configuration
USB/PS2 Transceiver
USB Pull-up
Enable
R/W
R/W
7
0
7
0
R/W
6
0
6
–
0
R/W
5
0
5
–
0
CC
IF VREG is not enabled or to the internally generated 3.3V when
Pending Interrupt [7:0]
R/W
4
0
4
–
0
Reserved
R/W
3
0
3
–
0
R/W
2
0
2
–
0
R/W
1
0
1
–
0
CY7C63310
CY7C638xx
CY7C639xx
Page 46 of 68
USB Force State
R/W
R/W
0
0
0
0