CY7C63903-PVXC Cypress Semiconductor Corp, CY7C63903-PVXC Datasheet - Page 50

• Manufacturer Part Number: CY7C63903-PVXC
• Description: IC USB PERIPHERAL CTRLR 28-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63903-PVXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-QSOP
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document 38-08035 Rev. *E
21.4
Table 21-4. Endpoint 1 and 2 Mode (EP1MODE – EP2MODE) [0x45, 0x46] [R/W]
21.4.1
Table 21-5. Endpoint 0 Data (EP0DATA) [0x50-0x57] [R/W]
Table 21-6. Endpoint 1 Data (EP1DATA) [0x58-0x5F] [R/W]
Table 21-7. Endpoint 2 Data (EP2DATA) [0x60-0x67] [R/W]
The three data buffers used to hold data for both IN and OUT
transactions. Each data buffer is 8 bytes long.
The reset values of the Endpoint Data Registers are unknown.
Bit 7: Stall
When this bit is set the SIE will stall an OUT packet if the Mode Bits are set to ACK-OUT, and the SIE will stall an IN packet if
the mode bits are set to ACK-IN. This bit must be clear for all other modes
Bit 6: Reserved
Bit 5: NAK Int Enable
This bit when set causes an endpoint interrupt to be generated even when a transfer completes with a NAK. Unlike enCoRe,
enCoRe II family members do not generate an endpoint interrupt under these conditions unless this bit is set
0 = Disable interrupt on NAK’d transactions
1 = Enable interrupt on NAK’d transaction
Bit 4: ACK’d Transaction
The ACK’d transaction bit is set whenever the SIE engages in a transaction to the register’s endpoint that completes with an
ACK packet.
This bit is cleared by any writes to the register
0 = The transaction does not complete with an ACK
1 = The transaction completes with an ACK
Bit [3:0]: Mode [3:0]
The endpoint modes determine how the SIE responds to USB traffic that the host sends to the endpoint. The mode controls how the
USB SIE responds to traffic and how the USB SIE will change the mode of that endpoint as a result of host packets to the endpoint.
The Endpoint 0 buffer is comprised of 8 bytes located at address 0x50 to 0x57
The Endpoint 1buffer is comprised of 8 bytes located at address 0x58 to 0x5F
The Endpoint 2 buffer is comprised of 8 bytes located at address 0x60 to 0x67
Read/Write
Read/Write
Read/Write
Read/Write
Default
Default
Default
Default
Field
Field
Field
Field
Bit #
Bit #
Bit #
Bit #
Endpoint 1 and 2 Mode
Endpoint 0, 1, and 2 Data Buffer
Unknown
Unknown
Unknown
Stall
R/W
R/W
R/W
R/W
7
0
7
7
7
Reserved
Unknown
Unknown
Unknown
R/W
R/W
R/W
R/W
6
0
6
6
6
NAK Int Enable
Unknown
Unknown
Unknown
R/W
R/W
R/W
R/W
5
0
5
5
5
R/C (Note 4)
Transaction
Endpoint 0 Data Buffer [7:0]
Endpoint 1 Data Buffer [7:0]
Endpoint 2 Data Buffer [7:0]
Unknown
Unknown
Unknown
ACK’d
R/W
R/W
R/W
4
0
4
4
4
Unlike past enCoRe parts the USB data buffers are only
accessible in the I/O space of the processor.
Unknown
Unknown
Unknown
R/W
R/W
R/W
R/W
3
0
3
3
3
Unknown
Unknown
Unknown
R/W
R/W
R/W
R/W
2
0
2
2
2
Mode[3:0]
Unknown
Unknown
Unknown
R/W
R/W
R/W
R/W
1
0
1
1
1
CY7C63310
CY7C638xx
CY7C639xx
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Unknown
Unknown
Unknown
R/W
R/W
R/W
R/W
0
0
0
0
0