CY7C63903-PVXC Cypress Semiconductor Corp, CY7C63903-PVXC Datasheet - Page 54

• Manufacturer Part Number: CY7C63903-PVXC
• Description: IC USB PERIPHERAL CTRLR 28-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63903-PVXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-QSOP
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document 38-08035 Rev. *E
24.0
0A–0B
07–09
11–13
Addr
0C
0D
0E
0F
2A
2B
2C
00
01
02
03
04
05
06
10
14
15
16
17
20
21
22
23
24
25
26
27
28
29
30
31
32
34
35
36
ITMRCLKCR
Register Summary
CPUCLKCR
TCAPINTE
TCAPINTS
LPOSCTR
CLKIOCR
FRTMRH
XOSCTR
FRTMRL
TCAP0R
TCAP1R
P0DATA
P1DATA
P2DATA
P3DATA
P4DATA
P02CR–
P05CR–
P14CR–
TCAP0F
TCAP1F
PITMRH
IOSCTR
PITMRL
TMRCR
P00CR
P01CR
P04CR
P06CR
P07CR
P10CR
P12CR
P13CR
P16CR
P17CR
P11CR
Name
P2CR
P3CR
P4CR
PIRH
PIRL
First Edge
Reserved
Reserved Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved Int Enable
Reserved USB CLK
SPI Use
32-KHz
Output
Output
Output
Power
TCAPCLK Divider
P0.7
P1.7
Hold
CLK
CLK
Low
TIO
7
foffset[2:0]
P0.6/TIO1 P0.5/TIO0 P0.4/INT2
/2 Disable
Reserved
Reserved
Reserved 32-KHz Bias Trim [1:0]
P1.6/SMI
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
SO
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
6
8-bit capture Prescale
Reserved
Reserved
Reserved
Reserved
Res
P1.5/SMO
USB CLK
Int Act
Int Act
Int Act
Int Act
Int Act
Int Act
Int Act
Int Act
Int Act
Int Act
Int Act
Int Act
Int Act
Int Act
Select
TCAPCLK Select
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
SI
5
P2.7–P2.2
P3.7–P3.2
TTL Thresh High Sink
TTL Thresh High Sink
TTL Thresh Reserved
TTL Thresh Reserved
TTL Thresh Reserved
TTL Thresh Reserved
TTL Thresh High Sink
TTL Thresh High Sink
TTL Thresh High Sink
TTL Thresh Reserved
P1.4/SCLK P1.3/SSEL P1.2/VREG
3.3V Drive
3.3V Drive
Free Running Timer [15:8]
Free Running Timer [7:0]
Prog Interval Timer [7:0]
XOSC
Select
Capture 0 Falling [7:0]
Capture 1 Falling [7:0]
Capture 0 Rising [7:0]
Capture 1 Rising [7:0]
4
Prog Interval [7:0]
Reserved
XOSC XGM [2:0]
Cap0 16bit
P0.3/INT1
High Sink
High Sink
Cap1 Fall
Cap1 Fall
Reserved
Enable
Enable
XOSC
Active
Active
ITMRCLK Divider
3
Reserved
Prog Interval Timer [11:8]
Open Drain
Open Drain
Open Drain
Open Drain
Open Drain
Open Drain
Open Drain
Open Drain
Open Drain
Open Drain
Open Drain
Open Drain
Open Drain
32-KHz Freq Trim [3:0]
Cap1 Rise
Cap1 Rise
P0.2/INT0
Gain[4:0]
Disable
Prog Interval [11:8]
Active
Active
EFTB
2
P4.3–P4.0
Reserved
P0.1/CLK-
PS/2 Pull-
up Enable
Reserved
Cap0 Fall
Cap0 Fall
Reserved
P1.1/D–
Pull-up
Enable
Pull-up
Enable
Pull-up
Enable
Pull-up
Enable
Pull-up
Enable
Pull-up
Enable
Pull-up
Enable
Pull-up
Enable
Pull-up
Enable
Pull-up
Enable
Pull-up
Enable
Pull-up
Enable
Active
Active
OUT
ITMRCLK Select
CLKOUT Select
1
P2.1–P2.0
P3.1–P3.0
CLK Select
Cap0 Rise
Cap0 Rise
P0.0/CLKI
P1.0/D+
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Active
Active
Mode
CPU
N
0
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
-bbbbbbb
-bbbbbbb
-bbbbbbb
-bbbbbbb
-bbbbbbb
-bbbbbbb
b-bbbbbb
--bbbbbb
-bbb-bbb
bbbbb---
---bbbbb
----bbbb
-bb---bb
-bb--b-b
----bbbb
----bbbb
----bbbb
----bbbb
---bbb-b
-bb----b
R/W
CY7C63310
CY7C638xx
CY7C639xx
Page 54 of 68
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00010000
00000000
000ddddd
000ddd0d
dddddddd
10001111
Default