RC82562EP Intel, RC82562EP Datasheet
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... Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual January 2003 Revision 1.0 ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. ...
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... Max_Lat / Min_Gnt (Offset 3E) ..............................................................................18 4.1.18 Power Management PCI Configuration Registers ................................................. 18 4.2 PCI Command Usage ......................................................................................................... 21 4.2.1 Memory Write and Invalidate ................................................................................. 22 4.2.2 Read Align ............................................................................................................. 23 4.2.3 Odd Byte Alignment Support ................................................................................. 23 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Contents iii ...
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... Special Control Register: Register 17.................................................................. 123 7.3.3 Clock Synthesis Test and Control Register: Register 18..................................... 124 7.3.4 100BASE-TX Receive False Carrier Counter: Register 19 ................................. 124 7.3.5 100Base-TX Receive Disconnect Counter: Register 20...................................... 124 iv Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual ...
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... EEPROM Read Timing Diagram ................................................................................................ 48 14 General Action Command Format .............................................................................................. 58 15 NOP Command Format .............................................................................................................. 59 16 Individual Address Setup Command Format ..............................................................................60 17 Configure Command Format ...................................................................................................... 61 18 Multicast Setup Command Format ............................................................................................. 80 19 Transmit Command Format........................................................................................................81 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Contents v ...
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... General Control Register ............................................................................................................ 56 34 General Status Register Location............................................................................................... 56 35 General Status Register ............................................................................................................. 56 36 Operation Codes ........................................................................................................................ 57 37 82557 Configuration Byte Map ................................................................................................... 62 38 82558 Configuration Byte Map ................................................................................................... 63 39 82559 Configuration Byte Map ................................................................................................... 64 vi Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual ...
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... Dump Data Structure ................................................................................................................ 149 66 IPCB Structure.......................................................................................................................... 153 67 IP Activation Bits (Byte 13) ....................................................................................................... 153 68 IP Activation Bits (Byte 12) ....................................................................................................... 153 69 IPCB Fields............................................................................................................................... 154 70 IPCB Structure Checksum Offload ........................................................................................... 156 71 IPCB Structure Large Send ......................................................................................................160 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Contents vii ...
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... Contents Revision History Date January 2003 viii Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Revision 1.0 Initial release. Description ...
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... Fast Ethernet controllers are highly similar, this manual documents the functionality of all devices and details the differences between the devices intended to be used as a tool to maintain and develop software for all devices in the Intel family of Fast Ethernet controllers. Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual ® ...
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... Document Conventions 1.2.1 Device References This document encompasses information for all members of the Intel Fast Ethernet controllers: 82551, 82550, 82559, 82558, 82557 and the 82562. The document convention, “8255x,” will be used to refer to all devices. In addition, there are specific references to the 82557 throughout this manual that pertains to all 8255x devices. Device- specific differences and exceptions will be documented ...
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... Paragraph alignment: Paragraph alignment implies that the physical addresses may only be aligned on 16-byte boundaries. In other words, the last nibble must Example: 02345ADC0h Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Introduction 3 ...
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... Introduction 4 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual ...
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... Mbps. The Intel 82555 is one possible TX solution. The block diagram below illustrates an Intel MAC with PHY. Figure 1. 82557 Network Interface Card Block Diagram Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual ® 8255x device support the ANSI/IEEE 802.3u standard for 100BASE- ® ...
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... PHY based flow control support when the internal 100BASE-TX PHY is used. • Advanced Configuration and Power Interface (ACPI) Specification and PCI Power Management Specification compliant. • Remote power up support (for Magic Packet*). 6 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual ...
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... The 82558, 82559, 82550 and 82551 contain an embedded PHY module. Although the PHY is internal for these devices, software still communicates to the PHY unit through the MDI port. For 10/100 Mbps connections, the 82557 can be used in conjunction with the Intel Mbps only connections, the 82557 can be interfaced to the Intel maintaining software compatibility to 100 Mbps solutions ...
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... Adapter and Controller Overview 8 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual ...
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... Device Power States Currently, operating systems only support the D0 and D3 power states. However, starting with the 82558, the Intel Fast Ethernet controller family supports all four power states as defined in the PCI Power Management Specification. These power states are named D0, D1, D2 and D3 the maximum powered state, and D3, the minimum powered state ...
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... During the D3 power state, the 82558 A-step does not maintain an active link. The 82558 B-step and later generation devices do not maintain a link PME is disabled or if the device does not have power. 10 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 13) and later devices also maintain an active link in the D3 state if PME Table 2, “Device ...
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... Subsystem ID 30 Expansion ROM Base Address Register 34 Reserved 38 Reserved 3C Max_Latency (FFh) DC Power Management Capabilities E0 Reserved Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Byte 3 Byte 2 Header Type Min_Grant (FFh) Data 4 Byte 1 Byte 0 Vendor ID Command Register Revision ID Latency Timer ...
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... Status Register (Offset 6) The Status Register is used to record status information for PCI bus related events. Its layout is shown below. The shaded bits are not used and are hard-wired Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 10 9 Command Bits Description “ ...
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... A-Step 82557 B-Step 82557 C-Step 82558 A-Step 82558 B-Step 82559 A-Step 82559 B-Step 82559 C-Step Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Description is always equal to 0 for the 82557. PCI Revision Intel Driver Revision ID Supported Supported 01h 2 ...
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... For the 82559, the value of this register is determined by a bit in the EEPROM. This register should read 00h for a standard Ethernet adapter, 00h. 14 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual PCI Revision Revision ID Supported 09h 2 ...
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... A device that wants a 1 Mbyte memory address space would set the most significant 12 bits of the base address register to be configurable, setting the other bits to 0. Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual PCI Interface ...
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... ROM. A 32-bit Expansion ROM Base Address Register at offset 30h in the PCI Configuration Space is defined to handle the address and size information for boot-time access to 16 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Table 3 describes the implementation of ...
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... For the 82257, this register is hard-wired to 0 since it does not support power management. For the 82558 this register is set to DCh if power management is enabled in the EEPROM. If power management is disabled, then this register is set to 0. For the 82559 and later Intel Fast Ethernet controllers, this register is hard-wired to DCh. 4.1.15 Interrupt Line (Offset 3C) The Interrupt Line register is an 8-bit register used to communicate interrupt line routing information ...
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... Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Description PME_Support. This five bit field indicates the power states in which the device may assert PME#. A value of 0b for any bit indicates that the function is not capable of asserting the PME# signal while in that power state ...
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... Since power management is not implemented in the 82557, this register is hard- coded to 0 for that device. For the 82558 and later devices this register acts according to the chart below. Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Description RO Reserved ...
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... CLK pin. Thus, if the Wake on LAN (WOL) bit in the EEPROM is set, the device will wake up the system upon receiving of Magic Packet*. 20 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Description PME Status. This bit is set upon a wake-up event from the link Read independent of the state of the PME_Enable bit ...
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... NOTE: The D1 and D2 power states are not currently supported by operating systems. 4.2 PCI Command Usage The table below lists the PCI commands that the various Intel Fast Ethernet controllers can use. Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Data Scale ...
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... Disconnect-C), the device issues a new cycle from the disconnected point using the MW command. If the disconnect occurs on a cache line boundary, the 22 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Name Circumstance Used TxCB “ ...
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... Odd Byte Alignment Support Various data structures have special memory alignment requirements. These alignment requirements are detailed in Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual (Section 6.4.2.3, “Configure (010b)”). Section 6.2.1, “LAN Controller Addressing PCI Interface (010b)” ...
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... PCI Interface 24 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual ...
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... Since the 82559 and later devices are capable of interfacing with different size EEPROMs (64 or 256 words), software determine the EEPROM size first using the “dummy zero mechanism” before it accesses the EEPROM after a reset. Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 5 25 ...
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... EEPROM Interface 26 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual ...
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... The SCB also holds pointers to a linked list of action commands called the CBL and a linked list of receive resources called the RFA. This type of structure is shown in the figure below. Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 6 27 ...
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... Management Data Interface (MDI) registers. This is achieved through the EEPROM Control Register and the MDI Control Register, respectively. These registers occupy offsets 0Ch through 14h of the CSR. 28 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 10/100 Mbps Device (8255x) Registers Command Block List (System Memory) Control Block ...
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... A 32-bit segmented scheme can be used as well by programming the appropriate 32-bit base address register and using the lower 16 bits of the 32-bit offset. This is illustrated in the table below. Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Effect on LAN Controller Resets all internal registers. A full initialization sequence is needed to make the device operational ...
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... As mentioned earlier, the 8255x data structures have special memory alignment requirements. The table below lists these requirements. Most of the structures listed in the table will be discussed in much greater detail in subsequent sections. 30 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Base Register 32-bit Offset Pointer CU Base (32-bit) ...
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... Accessing these higher offset areas in older devices has an unpredictable effect and may cause errors. Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Alignment Requirements Paragraph aligned (16-byte) Paragraph aligned (16-byte) Address allocated by the BIOS ...
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... CSR and I/O space for the CSR. Software may use either memory mapped or I/O mapped mode or even use them interchangeably. In most environments, memory mapped mode is the 32 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Lower Word 16 15 ...
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... The RU is not ready (RNR Interrupt). — A previously initiated read or write cycle to the MDI has been completed (MDI Interrupt). — Software has requested an interrupt (SWI Interrupt). Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface 33 ...
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... Note: The LAN controller latches interrupts internally. Interrupts are PCI compliant and level-triggered. Setting the interrupt acknowledge command for a non-pending interrupt does not cause any 34 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 16 15 Lower Word SCB Status Word ...
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... Bit 9 Reserved Bit 8 FCP Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Description This bit indicates that the CU finished executing a command with its interrupt bit set. The 82557 includes a TNO feature where the device can be configured to assert this interrupt when a transmit command is completed with a status of not okay ...
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... The 82558 and later devices also allow individual interrupt sources from within the device to be masked (this feature is not available in the 82557). 36 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Description This field contains the CU status (2 bits). Valid values are for this field are: ...
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... Bit 25 SI Bit 24 M Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Description The mask bits range from bit 31 to 26. Writing mask bit disables the 8255x (except the 82557) from generating an interrupt, or asserting the INTA# pin, due to that corresponding event ...
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... Bits 23:20 CUC Bit 19 Reserved 38 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Description This field contains the CU Command. Valid values for this field are: 0000 NOP. The no operation command does not affect the current state of the unit. ...
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... Dump and Reset Statistical Counters command in the SCB CUC field. The counters are internal to the device and are listed in the table below. Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Description This field contains the RU Command. Valid values are: 000 NOP ...
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... the no resources state fall into this category. If the device is 48 configured to save bad frames and the status of the received frame indicates that bad frame, this counter is not updated unless the resources state. 40 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual ...
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... The device increments the counters by internally reading them, incrementing them, and writing them back. This process is invisible to the CPU and PCI bus. In addition, the counters adhere to the following rules: Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface 41 ...
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... The Dword written as part of a Port command should include: • 16-byte aligned address value on the AD31:AD4 data bus pins. • Port function selection code on AD3:AD0 42 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Bits 15:0 (Lower Word) SCB Status Word SCB General Pointer PORT Offset ...
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... Figure 11. Self-Test Results Format 31 CROM Content Signature Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Pointer Field (Bits 31:4) Don't care Self-test results pointer (16 byte alignment) Don't care Dump area pointer (16 byte alignment) Dump area pointer (16 byte alignment) ...
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... A value of FFh indicates that the wake-up packet length exceeded the 120 bytes. In this case, only the first 120 bytes are posted. 2. Writes the Wake-up packet data starting at Dword 2. 44 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual (110b)”. D31 Reserved ...
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... EEPROM. There should be no other local bus activity at this time. Figure 12. EEPROM Control Register Table 21. EEPROM Control Register Bits Definitions Bit Symbol 23:20 19 EEDO Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Lower Word (D15:D0) SCB Status Word SCB General Pointer PORT Reserved ...
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... Write the EESK bit and wait the minimum SK low time. d. Read the EEDO bit, looking for the dummy 0 bit. 46 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Serial Data In. The value of this bit is written to the EEPROM when performing write operations. ...
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... Read a data bit from the EEDO bit. c. Write the EESK bit then wait the minimum SK low time. d. Repeat steps 4.a through 4.d an additional 15 times. 5. De-activate the EEPROM by writing the EECS bit. Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface 47 ...
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... Write the EESK bit then wait the minimum SK high time. b. Write the EESK bit then wait the minimum SK low time. c. Repeat steps 4.a through 4.c an additional 15 times. 5. De-activate the EEPROM by writing the EECS bit. 48 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual ...
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... MDI register using word or byte access, the data is latched only on the write to the most significant byte of the register, which is located at offset 13h. Thus, the high byte should be written last. Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Section 7.1, “Management Data Interface (MDI)” Initialization”. ...
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... PHY Address. PHY Register Address. NOTE: This value equals 1 for Intel PRO/100B TX and T4 adapters. Data write command, software places the data bits here and the device shifts them out to the PHY read command the device reads these bits serially from the ...
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... DMA, the register decrements until it reaches zero. At this point the register is set to the size of the next receive data buffer (HDS or RFD), and the receive DMA is restarted. Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Lower Word (D15:D0) SCB Status Word ...
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... ER interrupt does not guarantee that this frame will also generate an FR interrupt (in other words, the driver should not poll for the end of frame not set). If the 52 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Lower Word (D15:D0) SCB Status Word ...
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... RFD Xoff bit or if the driver writes 1 to the Xoff bit (bit 17). Reading this bit returns 0. • Bits 15:11 - Reserved. These bits are reserved. Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Lower Word (D15:D0) SCB Status Word SCB General Pointer ...
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... EEPROM Control Register Early Receive Interrupt Receive Byte Count Register PMDR The PMDR has evolved over time in the various Intel Fast Ethernet controllers. The PMDR bits for the 82558 and 82559 are described below. 54 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual ...
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... Table 32. General Control Register Location Upper Word (D31:D16) SCB Command Word EEPROM Control Register Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Default Description Valid for 82559 only. 0 Link Status Change Indication ...
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... EEPROM Control Register Early Receive Interrupt Receive Byte Count Register PMDR Reserved Table 35. General Status Register Bits Operation 7 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Lower Word (D15:D0) FC Xon/Xoff FC Threshold General Status Default Description PCI Reset 0 Reserved. ...
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... Load Microcode 110 Dump 111 Diagnose Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Default Description HDX / FDX. This bit indicates duplex mode half duplex (HDX) and 1 = full duplex (FDX 100 Mbps. This bit indicates the wire speed Mbps and 1 = 100 Mbps ...
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... If the I bit is set, the device sets a request for the CX interrupt the EL bit is set, after completion of the command the CU becomes idle. If the S bit is set, the CU becomes suspended. Otherwise, the CU requests the beginning of the next action 58 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual I 0000000000 CMD ...
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... After reading the command and determining NOP, the device CU performs the following sequence: 1. Begins execution of the NOP action command. 2. Prepares the status word with C equal to 1 and OK equal Completes the NOP action command. Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual I 0000000000 000 C This is the 32-bit address of the next command block ...
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... Bits 28:19 CMD (Bits 18:16) C (Bit 15) OK (Bit 13) Individual Address 60 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual I 0000000000 001 C IA 2nd Byte, IA 1st Byte IA 6th Byte, IA 5th Byte This is the 32-bit address of the next command block added to the CU base to obtain the actual address ...
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... Therefore, a complete configuration map for each device will be presented below. Bit descriptions for the configuration bits follow the configuration map. Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual I 0000000000 ...
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... CRS and 15 CDT FDX Pin 19 Enable Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Byte Count Transmit FIFO Limit Receive FIFO Limit Receive DMA Maximum Byte Count Transmit DMA Maximum Byte Count Discard CI Overrun 1 1 Interrupt Receive ...
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... FC Delay Most Significant Byte 18 1 Automatic 19 FDX Note: The shaded bits in the table above have different meaning for the 82558 B-step. Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Byte Count Transmit FIFO Limit Receive FIFO Limit Term 0 0 ...
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... Automatic 19 FDX 6.4.2.3.1 Configuration Parameters The interpretation of the fields from the configuration byte maps are: • BYTE 0. 64 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Byte Count Transmit FIFO Limit Receive FIFO Limit Term Write on CL ...
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... Table 40. 82557 Dual-Port FIFO Settings Configuration Value (Nibble Wide) Binary (Transmit Bits 6:4 & Receive Bits 3: Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Transmit FIFO Limit Dwords Bytes ...
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... This may yield lower PCI throughput in systems which are not extremely cache line oriented. This bit should therefore be set only in systems that are extremely cache line oriented Terminate Write on Cache Line disabled. 66 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual ...
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... These counters are only valid when this bit is set to 1. This bit enables both the receive and transmit DMA maximum byte counters. Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Section 4.2.2, “Read Align” ...
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... This bit is reserved on the 82557, and should be set to 1. For the 82558 or 82559, it determines the number of statistical counters that are dumped by the device when the Dump Statistical Counters or Dump and Reset Statistical Counters command is issued Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual ...
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... For the 82559, setting this bit to 1 causes the device to provide TCO statistical counters. In this case, the statistical counters are 24-Dword long structures with the last 4 Dwords. Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Section 6.4.2.5, “Transmit (100b)” ...
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... Recommended - 0 (unless reducing transmit latency is large concern). — Bits 2:1 - Underrun Retry. This field specifies the number of transmission retries after an underrun has occurred. 70 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Extended Statistical Statistics Counters Functionality Counters ...
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... It is valid on the 82558 or 82559 and used to disable the link operation of the device set to 1, the device will not receive data to or from the link set to 0, the Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface ...
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... This bit enables assertion of PME# upon a link status change event. The PME# signal is further gated by the PME enable bit in the PMCSR Disabled Enabled. 72 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Section 6.4.3.4, “No Buffer Performance Improvements (82558 ...
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... Table 43. Pre-amble Length D5 Default setting - 10b (7 bytes). Recommended - 10b. — Bit Source Address Insertion. This bit determines the source of the source address insertion (SA comes from internal device IA). Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual D4 Preamble Length byte ...
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... The ARP filter compares the value stored in offset 13 of the configuration block to the byte at offset ARP frame without a VLAN header and to byte 45 in ARP frames with a VLAN header. 74 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Configuration Block Configuration Offset ...
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... Wait After Win “Collision Backoff Modification in Switched 0 = Wait After Win disabled Wait After Win enabled. Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface Offset 13 Offset 14 IP Address Low ...
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... Default - 0 (disabled). Recommended - 0. — Bit 1 - Padding Enable. If this bit is set to 1, the device enables the padding mechanism. If the byte count of a transmitted frame is less than the minimum frame length, a padding 76 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual ...
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... Default - 0 (off) for the 82557 and 82558 A -step; 1 (on) for the 82558 B-step and 82559. Recommended - 1. Table 46. Full Duplex Functionality FDX PIN ENABLE Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual FORCE FDX State of FDX# (bit 7) (bit 6) ...
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... This bit takes effect only if the wake enable bit is set in the PMCSR. Default (82557 compatible). 78 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Register”). The flow control frame transmitted will carry Register”). The flow control frame transmitted will carry ...
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... Waits for the execution machine to complete its internal update of configuration registers. 6. Prepares the status word with and Completes the configuration action command. Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface 79 ...
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... I (Bit 29) Bits 28:19 CMD (Bits 18:16) C (Bit 15) OK (Bit 13) Multicast Count Multicast List 80 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual I 0000000000 011 C 1st Byte X This is the 32-bit address of the next command block added to the CU base to obtain the actual address. ...
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... Figure 19. Transmit Command Format Offset 00h EL S 04h Link Address (A31:A0) 08h Transmit Buffer Descriptor Array Address TBD Number Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual (Section 6.4.2.3, “Configure Command Word Bits 31:16 I CID 000 NC SF 100 Transmit Threshold Host Software Interface (010b)” ...
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... Address TBD Number 82 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual This is the 32-bit address of the next command block added to the CU base to obtain the actual address. If this bit is set to one, it indicates that this command block is the last one on the CBL. ...
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... Transmit Buffer #N Address Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual The transmit threshold defines the number of bytes that should be present in the controller's transmit FIFO before it starts transmitting the frame. The value is internally multiplied give a granularity of 8 bytes. For example, a value of 1 means the 82557 will start transmitting only when it has 8 bytes in its transmit FIFO ...
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... Begin transmission (depending on the transmit threshold value). 84 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual This is the starting address of the memory area that contains the data to be sent absolute 32-bit address. It does not add the CU base value to determine the physical address ...
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... The transmit command differs from other action commands. Generally, the action commands have parameters in one memory block. However, the transmit command may have parts of the parameters scattered in a linked list of buffers. The CU spontaneously pre-fetches the buffers in the list. Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface 85 ...
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... The transmit byte machine performs the following sequence: 1. Pre-amble bytes are transferred according to pre-amble length configuration parameter. 86 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual ...
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... The purpose of the delay is to avoid issuing this interrupt not required assumed that the interrupt is not required in the following cases: • The device was issued another action command and the CU returns to the active state. Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface 87 ...
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... Figure 21. Load Microcode Command Format Offset Command Word Bits 31:16 00h EL S 04h Link Address (A31:A0) 08h First Microcode Dword 260h 64th Microcode Dword 88 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual I 0000000000 101 C X Status Word Bits 15:0 OK XXXXXXXXXXXXX ...
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... Link Address (A31:A0) 08h Buffer Address Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual This is the 32-bit address of the next command block added to the CU base to obtain the actual address. If this bit is set to one, it indicates that this command block is the last one on the CBL. ...
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... FEXT RCV_RD Current Address Register (low) 90 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual This is the 32-bit address of the next command block added to the CU base to obtain the actual address. If this bit is set to one, it indicates that this command block is the last one on the CBL. ...
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... Configure Byte 18 35 Configure Byte 19 36 Configure Byte 20 37 Configure Byte 21 38 Reserved 39 Individual Address Register 1 40 Individual Address Register 2 41 Individual Address Register 3 42 Individual Address Register 4 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface ...
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... Hash Register 0 64 Hash Register 1 65 Hash Register 2 66 Hash Register 3 67 Hash Register 4 68 Hash Register 5 69 Hash Register 6 70 Hash Register Receive Length (high) 76 Receive Length (low) 77 – 79 Reserved 92 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual ...
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... DMA Arbitration Registers 83 – 85 Reserved 86 Micromachine Register File 31 87 Micromachine Register File 30 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Byte 3 Byte 2 Execution Status Port SCB CUC and SCB Interrupt Byte RUC Byte SCB CUC and SCB Interrupt Byte ...
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... Micromachine Bit Flag Array 4 122 Micromachine Bit Flag Array 3 123 Micromachine Bit Flag Array 2 124 Micromachine Bit Flag Array 1 125 Micromachine Bit Flag Array 0 94 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Byte 3 Byte 2 Byte 1 ...
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... Its format is illustrated below. Figure 23. Diagnose Command Format Offset Command Word Bits 31:16 00h EL S 04h Link Address (A31:A0) Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Byte 3 Byte 2 I 0000000000 111 C X Host Software Interface ...
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... The CSMA/CD module performs the self test procedure in two phases: phase 1 tests the counters and phase 2 tests the trigger logic. 96 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual This is the 32-bit address of the next command block added to the CU base to obtain the actual address. ...
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... In the simplified RFA structure, the data portion of the received frame (including the Ethernet header) is part of the RFD and is located in contiguous memory immediately after the size field in the RFD. The simplified memory structure is shown in the figure below. Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface 97 ...
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... EL (Bit 31) S (Bit 30) H (Bit 20) SF (Bit 19) C (Bit 15) OK (Bit 13) Status Bits (Bits 12:0) 98 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual RECEIVE FRAME AREA RFD RFD Sequential Sequential Data Buffer Data Buffer Command Word Bits 31:16 ...
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... Bit 3 This bit is reserved. Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual The link address is a 32-bit offset to the next RFD added to the RU base. The link address of the last frame can be used to form a cyclical link to the first RFD. ...
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... If discard short frames is enabled, any receive frame shorter than 64 bytes on the link (including padding and CRC) will be completely discarded. Although these frames are discarded, they are still counted in the short frame counter. 100 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Description Actual Count ...
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... RNR interrupt request is initiated and the state is changed to suspended the RU start request bit is set but the S bit is not, then the RU state is changed to ready and a new RFD is created. Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface 101 ...
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... The following equation and example demonstrate this: Example 1. 82559 Checksum Calculation Assume the following incoming Packet Type B Checksum = { where … 102 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual + … ...
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... If all interrupt bits are cleared, the 8255x clears its INTA# line. If the interrupt service routine is likely to process all pending interrupts, then all the bits can be acknowledged in one PCI write cycle. Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual ...
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... Reads the CB offset from the SCB (general pointer register) and saves pointer to the first CB in the CBL. 2. Becomes active and starts execution from the beginning of the CBL if the CU is not in the active state. 104 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual ...
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... Table 52. CU Activities Performed at the End of Execution EL Bit S Bit Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Table 51 and Table 52 illustrate the various state transitions. CU Start Action Start processing CB pointed to by SCB general pointer. Start processing CB pointed to by SCB general pointer ...
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... Idle No No Resources Resource due to No due to No RFDs RFDs Suspended Suspend Ready Prohibited 106 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual RU Start RU Resume Next Next Action Action State State Set Up Idle None RFD Set Up Prohibited ...
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... It stops discarding, goes to the READY state, gives up the pre-fetched current buffers, and sets up a new RFD. Setting up a new RFD uses the pointer to the next RFD to prepare to receive the next frame. Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface 107 ...
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... This can be accomplished by sending an indication to a transmitting station of an almost full receive buffer condition at a receiving station. 108 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual ...
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... Special DA (6 bytes bytes), Type (2 bytes), Command (2 bytes), Parameters (2 bytes), Pad (42 bytes), CRC (4 bytes). Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Host Software Interface Section 6.6.3, “Priority Aware Frame Based [Section 7.2.4, “Auto-Negotiation Advertisement ...
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... Transmission is restarted upon expiration of the pause timer or upon reception of a pause request with a time parameter of zero (also known as an XON frame). 6.6.2.3 Flow Control Functionality Note: The 82557 does not support flow control functionality. 110 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual S one byte Pre-amble bytes SFD ...
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... In this mode, the device sends a pause command and waits for the receive FIFO to empty. When it is empty, the device sends an XON command Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual (Section 6.4.2.3, “Configure (010b)” ...
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... ReStart Mode: Nothing further should be done. For convenience, flow control related configuration bits contains more detail) are described in the table below: 112 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual (Section 6.4.2.3, “Configure (010b)” ...
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... Flow Control Frame Format The pause and pause low flow control frames share the same frame format. illustrates a flow control frame. Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Map Location IEEE frame based transmit flow control. ...
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... Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Environments”) guarantees that the flow control frame will be Section 6.7, “Collision Backoff ...
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... Physical Layer Interface Intel Fast Ethernet adapters all have a physical layer (PHY) component that interfaces the network adapter to the wire. The MAC component of the adapter interfaces to the PHY component via the IEEE Media Independent Interface (MII). Sometimes it is necessary for software to access these PHY registers to properly configure the PHY ...
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... The Intel 82555-specific (and thus 82558 and 82559 specific as well) MDI registers are listed in the table below. (These registers also apply to the 82558 and 82559.) Table 57. 82555 MDI Register Set Register Address 10000 10001 ...
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The individual registers are defined in the following subsections using the following conventions: R: Read W: Write RO: Read only SC: Self clearing Note: The default values listed for the 82555 registers also apply to the registers in the embedded ...
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... Intel manufacturer OUI number is “00AA00h.”) The model number is a 6-bit value assigned by the manufacturer identifying the PHY model stored in bits 9:4 of register 3. (The Intel PHY model number is “010101.”) 118 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual ...
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... The revision number is a 4-bit value assigned by the manufacturer identifying the PHY revision number. The Intel devices use revision numbers “0000” through “0100.” The Intel 82558 has a revision ID number of 0000b, and the 82559, 0100b. The map below shows how the these three numbers (OUI, model and revision numbers) are mapped into the MDI registers ...
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Physical Layer Interface Bit Name 6 10BASE-T Full Duplex a 5 10BASE-T 4:0 Selector Field a. During normal operation, the driver (management agent) does not need to change this register value certain ability is not advertised, the respective ...
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Bit Name 15:5 Reserved 4 Parallel Detection Fault Link Partner Next Page 3 Able 2 Next Page Able 1 Page Received Link Partner Auto- 0 Negotiation Able 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual ...
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... Intel 82555 Specific Registers Note: The Intel MAC/PHY silicon devices (82558, 82559, 82550, and 82551) use the 82555 as the base for their integrated PHY units. Therefore, the information contained in this section and the following subsections apply to the all 8255x Fast Ethernet controllers except the 82557. ...
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Special Control Register: Register 17 Bit Name 15 Scrambler Bypass 14 4/5 Bypass 13 Force Transmit H Pattern 12 Force 34 Transmit Pattern RW 11 Good Link 9 MDI Tristate Dynamic Power Down 8 Disable Auto-Negotiation 7 Loopback 6 ...
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Physical Layer Interface 7.3.3 Clock Synthesis Test and Control Register: Register 18 Bit Name 15 Clock Timing 14 Clock Timing Break Down Timer 13 Enable Equalizer Probe Mode 12 Enable 10BASE-T Probe Mode 11 Enable 10:8 Reserved 4:0 PHY Address ...
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Receive Error Frame Counter: Register 21 Bit Name 15:0 Receive Error Frame 7.3.7 Receive Symbol Error Counter: Register 22 Bit Name 15:0 Symbol Error 7.3.8 100BASE-TX Receive EOF Error Counter: Register 23 Bit Name 15:0 Premature End of ...
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Physical Layer Interface 7.3.11 Equalizer Control and Status Register: Register 26 This register is used to control and monitor the operation of the 8255x PHY module equalizer (excluding the 82557 since it does not have an integrated PHY unit). Bits ...
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Opcode Command (bits 15:13) 011 Write to ASD configuration register 2 100 Read status register 101 Read jitter register 110 Read clock register 111 Reserved 7.3.12 Special Control Register: Register 27 Bit Name 15:0 Special Control Register 10/100 Mbps Ethernet ...
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Physical Layer Interface Table 60. LED Switch Control Bits ACTLED# Pin 2:0 000 Activity 001 Speed 010 Speed 011 Activity 100 Off 101 Off 110 On 111 On 7.4 Auto-Negotiation Functionality The PHY units of the 8255x devices (excluding the ...
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Table 61. Technology Ability Field Bit Assignments Bit Setting Technology 0 10BASE-T 1 10BASE-T Full Duplex 2 100BASE-TX 3 100BASE-TX Full Duplex 4 100BASE-T4 5 Reserved 6 Reserved 7 Reserved Table 62. Technology Priority Priority Technology 1 100BASE-TX Full Duplex ...
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... Vendor-Specific PHY Programming ® The Intel PRO/100B adapters are designed to support Intel and third-party PHYs using TX and T4 PHYs. The PHYs will be capable of auto-negotiation, but certain vendor specific programming hooks may be required to fully support these PHYs. These issues are addressed in this section. ...
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PHY Stand Alone (PHYSA) Mode Only the 82558 supports a special mode where its PHY unit can be used with an external controller through an MII-like interface. This mode is not fully MII compliant and should be used with ...
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Physical Layer Interface 132 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual ...
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... PHY Detection and Initialization It is recommended that drivers support the Intel Semiconductor* DP83840 devices as well as the integrated PHY units of the 82558, 82559, 82550, and 82551. In addition, a vendor specific routine should be executed immediately after PHY detection to initialize specific registers in other third party PHYs (for example, the DP83840) ...
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Programming Recommendations 8.1.3 NOS Specific Initialization Software should be written so that NOS specific interface routines call lower level driver routines. This will enable code re-use. 8.2 Transmit Processing Frame transmission is the most critical part of driver software, especially ...
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Interrupt Processing The 8255x supports latched level triggered interrupts. Interrupts can be shared in the system if the software and NOS support this mechanism. The SCB Command and Status words provide the necessary interface for interrupt management. The Mask ...
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Programming Recommendations 136 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual ...
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Wake-up Functionality Note: This appendix applies only to the 82558 and subsequent devices. Wake-up functionality was first introduced with the 82558 A-step. This component is capable of being brought out of a power managed stated by programming it to wake ...
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Wake-up Functionality External Auxiliary Clock Power Circuit Yes Yes No Yes Yes a. If the PME enable bit is set in the D0 state, the device will assert PME# for every wake-up event BIOS responsibility ...
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A.3.1 Auxiliary Power Support The LISTAT signal should be 0 after a hardware reset. For WOL mode, the default value after power up reset (ALTRST# is asserted) of the PME enable and status bits are: PME_Enable = 1 (wake up ...
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Wake-up Functionality A.4.1 Magic Packet* The 82558 and later generation controllers (except the 82559ER) are capable of generating a wake- up event upon reception of a Magic Packet. This feature is enabled by setting a bit in the Configuration command. ...
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Offset Hexadecimal Pattern 12 0806 X1, ... X4 Ethernet Type II frame msb Destination FF Address Source Address Frame 06 Type Data 01 IP address x4 The controller only filters the shaded fields in the frame format ...
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Wake-up Functionality Table 63. Fixed Wake-up Configuration Bits Configuration Bit Multicast Match Wake Enable IP Address Low Byte IP Address High Byte IA Match Wake Enable Magic Packet Wake-up Disable A.5 Link Status Event The controller may be configured to ...
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... Flexible Filtering Terminology Filter. A filter is a set of a signature and segments generated for a specific frame format. Each filter defines one frame that causes the controller to wake the system. The Intel Fast Ethernet controllers support 3 different filters. Segment. A segment defines a continuous sequence of bytes in a frame that should be filtered by the controller ...
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Wake-up Functionality A.6.3 Wake-up Packet Storage The device uses its internal registers for packet storage during power down mode. Only the first 124 bytes of a frame may be filtered and stored by the device. The residual section of the ...
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Pre-Defined Filters. The 82559 contains pre-defined filters for both Ethernet Type II and 802.2 snap. The 82559 distinguishes between these two types according to the MAC Type/Length field. The 82559 also handles VLAN tagging per packet filter as described ...
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Wake-up Functionality IA-Type IA-Match TCO There are two groups of pre-defined filters: — The NBH, ARP and IA-Type pre-defined filters each use the word match field. — The IA-Match and TCO pre-defined filters do not use the word match field. ...
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Flexible Filter Filter type Filter mask ( Dwords: DW0, DW1, DW2, DW3) Filter type The end of list bit indicates if this filter is the last active one. FIX Clearing this bit to 0 ...
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Wake-up Functionality A.7.2 CRC Word calculation of a Flexible Filter COEFFICIENTS = 0x04C11DB7; Signature = 0; for(n=i=0; n<128 & n<FrameLength; ++n) { if(Byte n of the Frame is in the Flexible Filter) { ShiftBy = (i modulo ...
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Table 65. Dump Data Structure Offset D31 0 1 2:N The sequence of events after a Dump Wake-up command that the 82559 performs are: 1. Write the byte count field at Dword 1. This field contains the actual number of ...
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Wake-up Functionality CLK is inactive and active. The deep power down state due to PME disable is enabled in the EEPROM. A.7.4.2 Power Down with Wake-up Capabilities The 82559 provides wake-up capabilities at all power ...
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The device statistic counters are corrupted during power down state. Therefore, the driver should clear the statistic counters by first issuing load dump counters address and then a dump and reset statistic counters the 82559 was at ...
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Wake-up Functionality 152 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual ...
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... Specific Information B This appendix applies to the Intel B.1 IPCB The IP command block (IPCB) is new and used to activate the new offloading features of the 82550 and 82551. The value of the command field for IPCB is 9h. The relevant aspects of the IPCB for each feature is described in the following subsections. This section summarizes the most useful combinations of the IPCB fields ...
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Specific Information Table 69. IPCB Fields Field Name Total TCP/UDP Payload TCP Header Offset IP Header Offset VLAN Reserved Scheduled Send Insert VLAN Hardware Parsing Large Send TCP/UDP Number TCP/UDP Checksum IP Checksum 154 10/100 Mbps Ethernet ...
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Table 69. IPCB Fields Scheduling Maximum TCP Payload Transmit Threshold Note: Using software parsing is only allowed with legal TCP/IP or UDP/IP packets. When software parsing is used, IP and TCP offsets in the IPCB must point to the appropriate ...
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Specific Information modes of operation. For instance, the driver must guarantee proper values for the Maximum TCP Payload in Large Send mode and VLAN length inclusion. Note: IP fragmentation is not supported by the 82550. Therefore, the ...
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B.2.2 IPCB Field Assignment The mode bits in the IP Activation field control the checksum operation of the transmit command. • IPv4 Checksum (1bit). When this bit is set to 1, the device is forced to perform checksum operation using ...
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Specific Information first byte of the TCP or UDP header. The controller reads this parameter when Hardware Parsing is clear and TCP/UDP checksum is set. Note: If TCP/UDP headset offset is specified, then the IP header offset ...
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Note: The partial checksum required by the 82550 is not the partial checksum passed by the Microsoft* IP stack per Microsoft offloading specification, v0.106. For TCP/UDP checksum computation, the 82550 requires that the whole frame is copied into its internal ...
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Specific Information Table 71. IPCB Structure Large Send Odd Word (D31:D16 CID (5 bits) L Maximum TCP Payload IP Activation (12 bits) TCP Header Offset (8 bits) Total TCP Payload (16 bits) Note: To ...
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Note: If the IPv4 checksum and TCP/UDP checksum are clear (checksum offload is not requested), frames will be transmitted without computing and replacing the checksum fields content. Therefore, the driver should set both bits so that the generated frames carry ...
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Specific Information — Fragment offset equals 0. This is expected but not checked by hardware. — IP options are not altered by hardware if they are present. — IP header checksum is calculated by the checksum hardware ...
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When the headers are finished, they are subject to checksum for processing. The rest of the transmission process is similar to transmission of a small send. This process repeats itself until the last frame is about to be transmitted. B.3.4.4 ...
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Specific Information way, it may read an extra TBD (or 8 bytes) after the last valid TBD. The driver is responsible for allocating enough memory for the TBD array. Otherwise, it needs to ensure that an extra ...
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B.4.1.1 Frame Types • Ethernet v2. If the Ethernet v2 type field equals 0800h, the first byte of IP header is expected right after the optional VLAN field. • SNAP. The 82550 and 82551 skip the DSAP and SSAP fields. ...