RC82562EP Intel, RC82562EP Datasheet - Page 132

• Manufacturer Part Number: RC82562EP
• Description: IC ETH 10/100 PLC DEV CTRL 64BGA
• Manufacturer: Intel

Specifications of RC82562EP

• Rohs Status: RoHS non-compliant
• Controller Type: Ethernet Controller
• Interface: IEEE 802.3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Current - Supply: -
• Operating Temperature: -
• Other names: 832361

Physical Layer Interface
7.3.3
7.3.4
7.3.5
124
100BASE-TX Receive False Carrier Counter: Register 19
Clock Synthesis Test and Control Register: Register 18
100Base-TX Receive Disconnect Counter: Register 20
Bit
15
14
13
12
11
10:8
4:0
Bit
15:0
Bit
15:0
Name
Clock Timing
Clock Timing
Break Down Timer
Enable
Equalizer Probe Mode
Enable
10BASE-T Probe Mode
Enable
Reserved
PHY Address
Name
Receive False Carrier
Name
Disconnect Event
10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
R / W
RW
SC
RW
SC
RW
RW
RO
R / W
RO
SC
R / W
RO
SC
Description
Clock Synthesizer Shift command. One shot
signaling YS10ACLK domain.
Can be active only when bit 14 is ‘0
Clock Synthesizer load command. One shot
signaling YS10ACLK domain.
Can be active only when bit 15 is ‘0
Logic 1 enables manipulate Break Down counter
with phya1, phya4 and test high.
Logic 1 enables the Equalizer output through the
Speed LED.
1 = Enable 10BASE-T dig outputs through the
LEDs
NOTE: This function is only present on the 82559.
These bits are reserved.
This field contains the PHY address.
Description
This register contains a 16-bit counter for false
carrier events. A false carrier event occurs when a
frame that does not start with “JK” is detected.
When the counter is full, additional false carrier
events are not counted. This counter is self-clearing
on read.
Description
This register contains a 16-bit counter for
disconnect events. The counter is incremented for
each frame detected in repeater mode that does
not start with a “JK.” When the counter is full,
additional disconnect events are not counted. This
counter is self-clearing on read.
Default
0
0
0
00001
Default
0
Default
0