RC82562EP Intel, RC82562EP Datasheet - Page 142

• Manufacturer Part Number: RC82562EP
• Description: IC ETH 10/100 PLC DEV CTRL 64BGA
• Manufacturer: Intel

Specifications of RC82562EP

• Rohs Status: RoHS non-compliant
• Controller Type: Ethernet Controller
• Interface: IEEE 802.3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Current - Supply: -
• Operating Temperature: -
• Other names: 832361

Programming Recommendations
8.1.3
8.2
8.3
134
NOS Specific Initialization
Software should be written so that NOS specific interface routines call lower level driver routines.
This will enable code re-use.
Transmit Processing
Frame transmission is the most critical part of driver software, especially in the server
environment. The 8255x supports dynamic chaining that allows frames to be chained to the active
transmit queue, even as the device processes frames in the queue. A simplified pseudo code flow
follows:
For dynamic chaining:
Frame Reception
The 8255x supports early receive interrupts only in the simplified memory model. It should be
noted that:
1. TxCBs should be initialized in a static circularly linked list at initialization time. Subsequently,
2. The device can be configured to generate interrupts in one of 2 ways:
•
•
software should not change these links. The 8255x remembers the next CB link if it suspends.
When a new CU Resume is issued, it follows the link to the next CB without accessing host
memory to read the next link.
The 8255x generates an interrupt when a frame is received from the wire. If early receive
interrupts are enabled, the first interrupt is generated after HDS bytes are deposited in host
memory and the second (final) interrupt is generated when the frame is fully received in
memory. Software cannot selectively disable these interrupts.
An RNR interrupt is generated on the first frame that the device fails to transfer to host
memory due to a condition of unavailable resources.
a. If the device is configured to generate CNA interrupts, an interrupt is generated when the
b. If interrupts are not desired each time the CU suspends, the 8255x can be configured for
CU becomes inactive as a result of entering the suspended state. If a CU Resume
command is issued, when the CU actively transmits the current last TxCB the 8255x re-
reads the current last TxCB S bit. If the S bit is still set, it ignores the CU Resume
command. If the bit is reset, it proceeds to execute the next TxCB.
CI interrupts. In this case, an interrupt is generated only when the CU encounters a TxCB
with the I bit set.
Get free TxCB
10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Set the S bit in the TxCB;
Set up other fields in the TxCB;
Reset S bit in the previous TxCB;
Wait for previous command to be accepted by the 8255x (SCB command = 0);
CU_RESUME