RC82562EP Intel, RC82562EP Datasheet - Page 65

• Manufacturer Part Number: RC82562EP
• Description: IC ETH 10/100 PLC DEV CTRL 64BGA
• Manufacturer: Intel

Specifications of RC82562EP

• Rohs Status: RoHS non-compliant
• Controller Type: Ethernet Controller
• Interface: IEEE 802.3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Current - Supply: -
• Operating Temperature: -
• Other names: 832361

6.4
6.4.1
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Table 35. General Status Register
Table 36. Operation Codes
Shared Memory Structures
The 8255x shared memory structures consist of the Command Block List (CBL) and the Receive
Frame Area (RFA) and are controlled by the SCB portion of the CSR. The SCB is internal to the
device while the CBL and RFA reside in main system memory.
Action Commands and Operating Modes
In addition to SCB control commands, the device can be controlled with action commands. This
section lists all the action commands that can be a part of the CBL. Each command contains a
command field, status and control fields, a link to the next action command, and command specific
parameters. There are three basic types of action commands: device configuration and setup,
transmission, and diagnostics. Alignment requirements are detailed in
Requirements for 8255x Data
Bits
2
1
0
Opcode
000
001
010
011
100
101
110
111
Operation
R
R
R
Name
NOP
Individual
Address Setup
Configure
Multicast
Address Setup
Transmit
Load Microcode
Dump
Diagnose
Default
Description
This command results in no action by the device other than the normal
command processing such as fetching the command and decoding the
command field.
This command is used to load the device unique address. The unique address is
contained in the parameter field of the command.
The configure command is used to load the device with its operating
parameters. Upon reset, the device initializes to the IEEE 802.3 based
parameters, with the exception of choosing either the PHY interface mode (for
example, MII). If the user wishes to use any other values, the configure
command is used.
This command allows the programmer to setup one or more multicast or
multiple individual addresses in the device. These addresses are located in the
parameter field of the command.
One transmit command is used to send a single frame. If more than one frame
needs to be sent, the host CPU can link multiple transmit commands together.
This command downloads microcode to the device.
Note: Documentation for microcode is beyond the scope of this manual.
This command causes the device to dump its internal registers into memory.
The registers included are those loaded by the configure and address setup
commands, plus status and other internal working registers.
The diagnose command puts the device CSMA/CD subsystem through a self-
test procedure and reports the result of the internal test.
Structures”.
Description
HDX / FDX. This bit indicates duplex mode: 0 = half duplex (HDX) and 1
= full duplex (FDX).
10 / 100 Mbps. This bit indicates the wire speed: 0 = 10 Mbps and 1 =
100 Mbps.
Link Status Indication. This bit indicates the status of the link: 0 = link
down and 1 = link up.
Table 10, “Alignment
Host Software Interface
57