RC82562EP Intel, RC82562EP Datasheet - Page 86

• Manufacturer Part Number: RC82562EP
• Description: IC ETH 10/100 PLC DEV CTRL 64BGA
• Manufacturer: Intel

Specifications of RC82562EP

• Rohs Status: RoHS non-compliant
• Controller Type: Ethernet Controller
• Interface: IEEE 802.3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Current - Supply: -
• Operating Temperature: -
• Other names: 832361

Host Software Interface
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Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
— Bit 6 - Force Full Duplex. This bit forces the device to operate in full duplex mode.
— Bit 5 - Reject FC (address filtering of full duplex transmit flow control frames). This bit is
— Bit 4 - Full Duplex Restart Flow Control. This bit is reserved on the 82557 and should be
— Bit 3 - Full Duplex Restop Flow Control. This bit is reserved on the 82557 and should be
— Bit 2 - Full Duplex Transmit Flow Control Disable. This bit is reserved on the 82557 and
— Bit 1 - Magic Packet Wake-up disable. This bit is reserved on the 82557 and 8259ER and
Transmit and receive execution can be active simultaneously. CRS is only a receive
activity indicator. Minimum reception spacing between back to back frames is two bytes.
Default - 0 - off.
Recommended - 0 (1 if the user specifies a valid override).
reserved on the 82557, and should be set to 0.
When this bit is set on the 82558 or 82559, received flow control frames will not be
passed to memory, regardless of any address mechanism they might pass. This bit has no
effect on the action taken upon reception of such a frame.
Default - 0 (82557 compatible).
Recommended - 0.
set to 0.
When this bit is set on the 82558 or 82559, it enables transmissions of flow control frames
to the peer station in order to stop its transmissions. The sending of such a frame is
triggered by the high threshold parameter, as set in the flow control threshold register
(Section 6.3.8, “Flow Control
the configured flow control delay value in the time field. When the receive FIFO is empty,
another flow control frame is sent with the value 0 in the time field.
Default - 0 (82557 compatible).
Recommended - 0.
set to 0.
When this bit is set on the 82558 or 82559, it enables transmissions of flow control frames
to the peer station in order to stop its transmissions. The sending of such a frame is
triggered by the high threshold parameter, as set in the flow control threshold register
(Section 6.3.8, “Flow Control
the configured flow control delay value in the time field. When this delay expires, the
device checks the receive FIFO state. If the FIFO is not empty, another flow control frame
is sent.
Default - 0 (82557 compatible).
Recommended - 0.
should be set to 0.
When this bit is 0 on the 82558 or 82559, it enables the transmit flow to be paused by
incoming flow control commands. Flow control commands come from the link as special
flow control frames with a time parameter. In this mode, upon reception of such a frame,
the device pauses transmissions according to the time parameter.
Default - 0 (82557 compatible).
Recommended - 0.
should be set to 0 for those devices.
When this bit is set on the 82558 or 82559, it disables the assertion of a special wake-up
signal upon reception of a Magic Packet* frame (which is a frame with certain predefined
fields). This bit takes effect only if the wake enable bit is set in the PMCSR.
Default: 0 - on (82557 compatible).
Register”). The flow control frame transmitted will carry
Register”). The flow control frame transmitted will carry