RC82562EP Intel, RC82562EP Datasheet - Page 75

• Manufacturer Part Number: RC82562EP
• Description: IC ETH 10/100 PLC DEV CTRL 64BGA
• Manufacturer: Intel

Specifications of RC82562EP

• Rohs Status: RoHS non-compliant
• Controller Type: Ethernet Controller
• Interface: IEEE 802.3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Current - Supply: -
• Operating Temperature: -
• Other names: 832361

Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
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BYTE 4.
Bits 6:0 - Receive DMA Maximum Byte Count. This byte indicates the maximum number of
receive DMA PCI transfers that will be completed before internal arbitration. The counter has
a 4 cycle resolution. This counter is useful in throttling back the receive DMA in order to let
other device DMA channels, such as the transmit DMA, CU DMA, or RU DMA, complete
PCI cycles. For instance, if the counter is set to 4, the receive DMA will only do a 16-cycle
PCI transfer if one of the other internal DMA channels also wants to initiate a transfer. If no
other internal DMA channels are requesting a transfer, the receive DMA may run an extended
PCI burst. In order for this counter to be enabled, the DMA maximum byte count enable bit
(byte 5, bit 7) must be set. If the enable bit is not set, the receive DMA will continue until it is
finished (no other DMA unit can pre-empt it).
Note:
Default - 0.
Recommended - 0.
BYTE 5.
— Bit 2 - Read Alignment Enable. This bit is reserved on the 82557 and should be set to 0.
— Bit 0 - MWI Enable. This bit is reserved on the 82557 and should be set to 0.
— Bit 7 - DMA Maximum Byte Count Enable. Bit 7 enables the receive and transmit DMA
1 = Terminate Write on Cache Line enabled.
Default - 0 (Terminate Write on Cache Line disable).
Recommended - 0.
However, when this bit is set on the 82558 and later generation controllers, the device
attempts to align its read accesses to cache lines. This may yield lower PCI throughput in
systems that are not extremely cache line oriented. Thus, this bit should be set only in
systems that are extremely cache line oriented. More information of the read alignment
capability is detailed in
0 = Read Alignment disabled.
1 = Read Alignment enabled.
Default - 0 (Read Alignment disabled).
Recommended - 0.
However, for the 82558 and later generation controllers, it enables the device to perform
Memory Write and Invalidate (MWI) cycles on the PCI bus. If both this bit and the MWI
enable bit in the PCI command register are both set, then the device attempts to perform
MWI cycles when writing data to system memory. If either this bit or the MWI enable bit
in the PCI command register are clear, the device will not perform MWI cycles. A more
detailed description of MWI can be found in
Invalidate”.
0 = MWI disabled. The device will not perform MWI cycles even if it is permitted by the
PCI command register.
1 = MWI enabled. The device will perform MWI cycles if it is permitted by the PCI
command register.
Default - 0 (MWI disabled).
Recommended - 1.
maximum byte count enable counters. These counters are only valid when this bit is set to
1. This bit enables both the receive and transmit DMA maximum byte counters.
If this counter is enabled and set to zero, then the receive DMA may be pre-empted
almost immediately.
Section 4.2.2, “Read
Align”.
Section 4.2.1, “Memory Write and
Host Software Interface
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