RC82562EP Intel, RC82562EP Datasheet - Page 51

• Manufacturer Part Number: RC82562EP
• Description: IC ETH 10/100 PLC DEV CTRL 64BGA
• Manufacturer: Intel

Specifications of RC82562EP

• Rohs Status: RoHS non-compliant
• Controller Type: Ethernet Controller
• Interface: IEEE 802.3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Current - Supply: -
• Operating Temperature: -
• Other names: 832361

6.3.3.1
6.3.3.2
Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Table 18. Port Selection Function
Figure 11. Self-Test Results Format
The port Dword may be written as a 32-bit entity, two 16-bit entities, or 4 8-bit entities. In the latter
case, the device accepts only the port command after the high byte (offset Bh) is written; therefore,
the high byte should be written last. Four different port commands are supported in the 82557 and
82558 devices. The 82559 and later generation controllers support an additional command, Dump
Wake-up.
PORT Software Reset
The Port Software Reset is synonymous with the software reset and is used to issue a complete
reset to the device. Software must wait for ten system clocks and five transmit clocks before
accessing the SCB registers again. (This may be a conservative 10 µs delay loop in software.) A
software reset clears the device CSR and the PCI master block internal registers. It also requires the
device to be completely re-initialized.
PORT Self-test
The controller self-test begins by issuing an internal selective reset and running a general internal
self-test of the device. The self-test function can be used to test the device micromachine
functionality, internal registers and internal ROM. After the self-test is completed, the results are
written to memory. The device provides the results of the self-test at the address specified by the
self-test port command. The format of the self-test results is shown in
command checks the following blocks:
Software Reset
Self-test
Selective Reset
Dump
Dump Wake-up
31
CROM Content Signature
0 0
•
•
•
ROM. The contents of the entire ROM are sequentially read into a Linear Feedback Shift
Register (LFSR). The LFSR compresses the data and produces a signature unique to one set of
data. The results of the LFSR are then compared to a known good ROM signature. The pass or
fail result and the LFSR contents are written into the address specified by the self-test port
command.
Parallel Registers: The micromachine performs write and read operations to all internal
parallel registers and checks the contents for proper values. The pass or fail result is then
written into the address specified by the self-test port command.
Diagnose: The micromachine issues an internal diagnose command to the serial subsystem.
The pass or fail result of the diagnose command is written into the address specified by the
self-test port command.
Function
0 0
0 0
0 0
Odd Word
Don't care
Self-test results pointer (16 byte alignment)
Don't care
Dump area pointer (16 byte alignment)
Dump area pointer (16 byte alignment)
0 0
0 0
Pointer Field (Bits 31:4)
0 0
0 0
16
15
0 0
0 S
0 0
Opcode (Bits 3:0)
Even Word
0 0
Figure
Host Software Interface
0000
0001
0010
0011
0111
0 0
11. The self-test
D 0
M R
0 0
43
0