ISP1505CBSGE ST-Ericsson Inc, ISP1505CBSGE Datasheet - Page 12

• Manufacturer Part Number: ISP1505CBSGE
• Description: IC ULPI TRANSCEIVER 24-HVQFN
• Manufacturer: ST-Ericsson Inc
• Type: Transceiverr

Specifications of ISP1505CBSGE

• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 4.5 V
• Mounting Type: Surface Mount
• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• For Use With: ISP1505CBS T&MT KIT - EVAL KIT FOR ISP1505 IC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Other names: ISP1505CBS; ISP1505CBS

NXP Semiconductors
ISP1505A_ISP1505C_3
Product data sheet
7.10.9.1 RESET_N
7.10.9.2 PSW_N
7.10.7 REG3V3 and REG1V8
7.10.8 XTAL1 and XTAL2
7.10.9 RESET_N/PSW_N
Regulator output voltage. These supplies are used to power the ISP1505 internal digital
and analog circuits, and must not be used to power external circuits.
For correct operation of the regulator, it is recommended that you connect REG3V3 and
REG1V8 to decoupling capacitors. For an example, see
XTAL1 is the crystal input, and XTAL2 is the crystal output. The allowed frequency on the
XTAL1 pin depends on the ISP1505 product version.
If the link requires a 60 MHz clock from the ISP1505, then either a crystal must be
attached, or a clock of the same frequency must be driven into XTAL1, with XTAL2 left
floating.
If a crystal is attached, it requires external load capacitors to GND on each terminal of the
crystal. For details, see
If at any time the system wants to stop the clock on XTAL1, the link must first put the
ISP1505 into low-power mode. The clock on XTAL1 must be restarted before low-power
mode is exited.
This pin provides two optional functions. If neither function is used, this pin must be
connected to V
An active LOW asynchronous reset pin that resets all circuits in the ISP1505. The
ISP1505 contains an internal power-on reset circuit, and therefore using the RESET_N
pin is optional. If RESET_N is not used, it must be connected to V
For details on using RESET_N, see
PSW_N is an active LOW, open-drain output pin. This pin can be connected to an active
LOW, external V
power source. An external pull-up resistor, R
pin is open-drain, allowing ganged-mode power control for multiple USB ports. For
application details, see
To use the PSW_N pin, the link must disable the reset input by setting the
IGNORE_RESET bit in the Power Control register to logic 1. This will ensure that PSW_N
is not misinterpreted as a reset.
If the link is in host mode, it can enable the external V
DRV_VBUS_EXT bit in the OTG Control register to logic 1. The ISP1505 will drive
PSW_N to LOW to enable the external V
overcurrent condition (the V
V
BUS
supply by setting DRV_VBUS_EXT to logic 0.
CC(I/O)
BUS
switch or charge pump enable circuit to control the external V
.
Rev. 03 — 26 August 2008
Section
Section
BUS
16.
state in RXCMD is not 11b), it must disable the external
16.
Section
ULPI HS USB host and peripheral transceiver
BUS
9.3.2.
pullup
power source. If the link detects an
ISP1505A; ISP1505C
, is required when PSW_N is used. This
BUS
Section
power source by setting the
16.
CC(I/O)
© NXP B.V. 2008. All rights reserved.
.
BUS
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