ISP1505CBSGE ST-Ericsson Inc, ISP1505CBSGE Datasheet - Page 52

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ISP1505CBSGE

Manufacturer Part Number
ISP1505CBSGE
Description
IC ULPI TRANSCEIVER 24-HVQFN
Manufacturer
ST-Ericsson Inc
Type
Transceiverr
Datasheet

Specifications of ISP1505CBSGE

Protocol
USB 2.0
Voltage - Supply
3 V ~ 4.5 V
Mounting Type
Surface Mount
Package / Case
24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
For Use With
ISP1505CBS T&MT KIT - EVAL KIT FOR ISP1505 IC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
Other names
ISP1505CBS
ISP1505CBS
NXP Semiconductors
Table 41.
ISP1505A_ISP1505C_3
Product data sheet
Bit
7 to 4
3
2
1
0
Symbol
-
BVALID_FALL
BVALID_RISE
-
IGNORE_RESET
Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit description
10.2 Extended register set
Addresses 00h to 3Fh of the extended register set directly map to the immediate set. This
means a read, write, set or clear operation to these extended addresses will operate on
the immediate register set.
Addresses 40h to FFh are not implemented. Operating on these addresses may result in
undefined behavior of the PHY.
Description
reserved; the link must never write logic 1 to these bits.
BVALID Fall: Enables RXCMDs for HIGH-to-LOW transitions on BVALID. When BVALID
changes from HIGH to LOW, the ISP1505 will send an RXCMD to the link with the ALT_INT
bit set to logic 1.
This bit is optional and is not necessary for OTG devices. This bit is provided for debugging
purposes. The session valid comparator should be used instead.
BVALID Rise: Enables RXCMDs for LOW-to-HIGH transitions on BVALID. When BVALID
changes from LOW to HIGH, the ISP1505 will send an RXCMD to the link with the ALT_INT
bit set to logic 1.
This bit is optional and is not necessary for OTG devices. This bit is provided for debugging
purposes. The session valid comparator should be used instead.
reserved
Ignore Reset: Selects between the RESET_N and PSW_N functions of the
RESET_N/PSW_N pin. The link must set this bit to logic 1, if PSW_N is used in a ganged
mode configuration.
0b — The RESET_N/PSW_N pin behaves as an active-LOW reset input (RESET_N). This is
the default setting.
1b — The RESET_N/PSW_N pin behaves as an active-LOW power switch output (PSW_N).
Rev. 03 — 26 August 2008
ULPI HS USB host and peripheral transceiver
ISP1505A; ISP1505C
© NXP B.V. 2008. All rights reserved.
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