ISP1505CBSGE ST-Ericsson Inc, ISP1505CBSGE Datasheet - Page 16

• Manufacturer Part Number: ISP1505CBSGE
• Description: IC ULPI TRANSCEIVER 24-HVQFN
• Manufacturer: ST-Ericsson Inc
• Type: Transceiverr

Specifications of ISP1505CBSGE

• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 4.5 V
• Mounting Type: Surface Mount
• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• For Use With: ISP1505CBS T&MT KIT - EVAL KIT FOR ISP1505 IC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Other names: ISP1505CBS; ISP1505CBS

NXP Semiconductors
Table 4.
Table 5.
ISP1505A_ISP1505C_3
Product data sheet
Signal
Reserved
INT
Reserved
Signal
TX_ENABLE
TX_DAT
TX_SE0
INT
RX_DP
RX_DM
RX_RCV
Reserved
Signal mapping during low-power mode
Signal mapping for 6-pin serial mode
Maps to
DATA2
DATA3
DATA[7:4]
8.1.3 6-pin full-speed or low-speed serial mode
8.1.4 3-pin full-speed or low-speed serial mode
Maps to
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
If the link requires a 6-pin serial interface to transmit and receive full-speed or low-speed
USB data, it can set the ISP1505 to 6-pin serial mode. In 6-pin serial mode, the DATA[7:0]
bus definition changes to that shown in
the 6PIN_FSLS_SERIAL bit in the Interface Control register to logic 1. To exit 6-pin serial
mode, the link asserts STP. This is provided primarily for links that contain legacy
full-speed or low-speed functionality, providing a more cost-effective upgrade path to
high-speed. An interrupt pin is also provided to inform the link of USB events. If the link
requires CLOCK to be running during 6-pin serial mode, the CLOCK_SUSPENDM
register bit must be set to logic 1.
For more information on 6-pin serial mode enter and exit protocols, refer to UTMI+ Low
Pin Interface (ULPI) Specification Rev. 1.1 .
If the link requires a 3-pin serial interface to transmit and receive full-speed or low-speed
USB data, it can set the ISP1505 to 3-pin serial mode. In 3-pin serial mode, the data bus
definition changes to that shown in
3PIN_FSLS_SERIAL bit in the Interface Control register to logic 1. To exit 3-pin serial
mode, the link asserts STP. This is primarily provided for links that contain legacy
full-speed or low-speed functionality, providing a more cost-effective upgrade path to
high-speed. An interrupt pin is also provided to inform the link of USB events. If the link
requires CLOCK to be running during 3-pin serial mode, the CLOCK_SUSPENDM
register bit must be set to logic 1.
For more information on 3-pin serial mode enter and exit protocols, refer to UTMI+ Low
Pin Interface (ULPI) Specification Rev. 1.1 .
Direction
O
O
O
Direction
I
I
I
O
O
O
O
O
Description
reserved; the ISP1505 will drive this pin to LOW
active HIGH interrupt indication; will be asserted whenever any unmasked
interrupt occurs
reserved; the ISP1505 will drive these pins to LOW
Rev. 03 — 26 August 2008
Description
active HIGH transmit enable
transmit differential data on DP and DM
transmit single-ended zero on DP and DM
active HIGH interrupt indication; will be asserted whenever any
unmasked interrupt occurs
single-ended receive data from DP
single-ended receive data from DM
differential receive data from DP and DM
reserved; the ISP1505 will drive this pin to LOW
…continued
Table
Table
ULPI HS USB host and peripheral transceiver
6. To enter 3-pin serial mode, the link sets the
ISP1505A; ISP1505C
5. To enter 6-pin serial mode, the link sets
© NXP B.V. 2008. All rights reserved.
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