ISP1505CBSGE ST-Ericsson Inc, ISP1505CBSGE Datasheet - Page 73

• Manufacturer Part Number: ISP1505CBSGE
• Description: IC ULPI TRANSCEIVER 24-HVQFN
• Manufacturer: ST-Ericsson Inc
• Type: Transceiverr

Specifications of ISP1505CBSGE

• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 4.5 V
• Mounting Type: Surface Mount
• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• For Use With: ISP1505CBS T&MT KIT - EVAL KIT FOR ISP1505 IC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Other names: ISP1505CBS; ISP1505CBS

NXP Semiconductors
24. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. LINESTATE[1:0] encoding for upstream
Table 11. LINESTATE[1:0] encoding for downstream
Table 12. Encoded V
Table 13. V
Table 14. Encoded USB event signals . . . . . . . . . . . . . .26
Table 15. PHY pipeline delays . . . . . . . . . . . . . . . . . . . . .30
Table 16. Link decision times . . . . . . . . . . . . . . . . . . . . .31
Table 17. Immediate register set overview . . . . . . . . . . .43
Table 18. Extended register set overview . . . . . . . . . . . .43
Table 19. Vendor ID Low register (address R = 00h)
Table 20. Vendor ID High register (address R = 01h)
Table 21. Product ID Low register (address R = 02h)
Table 22. Product ID High register (address R = 03h)
Table 23. Function Control register (address R =
Table 24. Function Control register (address R =
Table 25. Interface Control register (address R =
Table 26. Interface Control register (address R =
Table 27. OTG Control register
Table 28. OTG Control register
Table 29. USB Interrupt Enable Rising Edge register
Table 30. USB Interrupt Enable Rising Edge register
Table 31. USB Interrupt Enable Falling Edge register
ISP1505A_ISP1505C_3
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
ULPI signal description . . . . . . . . . . . . . . . . . .13
Signal mapping during low-power mode . . . . .14
Signal mapping for 6-pin serial mode . . . . . . .15
Signal mapping for 3-pin serial mode . . . . . . .16
Operating states and their corresponding
resistor settings . . . . . . . . . . . . . . . . . . . . . . . .16
TXCMD byte format . . . . . . . . . . . . . . . . . . . . .22
RXCMD byte format . . . . . . . . . . . . . . . . . . . . .23
facing ports: peripheral . . . . . . . . . . . . . . . . . .23
facing ports: host . . . . . . . . . . . . . . . . . . . . . . .24
typical applications . . . . . . . . . . . . . . . . . . . . . .25
bit description . . . . . . . . . . . . . . . . . . . . . . . . .44
bit description . . . . . . . . . . . . . . . . . . . . . . . . .44
bit description . . . . . . . . . . . . . . . . . . . . . . . . .44
bit description . . . . . . . . . . . . . . . . . . . . . . . . .44
04h to 06h, W = 04h, S = 05h, C = 06h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
04h to 06h, W = 04h, S = 05h, C = 06h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
07h to 09h, W = 07h, S = 08h, C = 09h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
07h to 09h, W = 07h, S = 08h, C = 09h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
(address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh,
C = 0Ch) bit allocation . . . . . . . . . . . . . . . . . . .46
(address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh,
C = 0Ch) bit description . . . . . . . . . . . . . . . . . .47
(address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh,
C = 0Fh) bit allocation . . . . . . . . . . . . . . . . . . .47
(address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh,
C = 0Fh) bit description . . . . . . . . . . . . . . . . . .48
(address R = 10h to 12h, W = 10h, S = 11h,
BUS
indicators in RXCMD required for
BUS
voltage state . . . . . . . . . . . . . .24
Rev. 03 — 26 August 2008
Table 32. USB Interrupt Enable Falling Edge register
Table 33. USB Interrupt Status register
Table 34. USB Interrupt Status register
Table 35. USB Interrupt Latch register
Table 36. USB Interrupt Latch register
Table 37. Debug register (address R = 15h)
Table 38. Debug register (address R = 15h)
Table 39. Scratch register (address R = 16h to 18h,
Table 40. Power Control register
Table 41. Power Control register
Table 42. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 43. Recommended operating conditions . . . . . . . . 53
Table 44. Static characteristics: supply pins . . . . . . . . . . 54
Table 45. Static characteristics: digital pins
Table 46. Static characteristics: pin V
Table 47. Static characteristics: analog I/O pins
Table 48. Static characteristics: V
Table 49. Static characteristics: V
Table 50. Static characteristics: resistor reference . . . . . 57
Table 51. Dynamic characteristics: reset and clock . . . . 58
Table 52. Dynamic characteristics: digital I/O pins . . . . . 58
Table 53. Dynamic characteristics: analog I/O pins
Table 54. Recommended bill of materials . . . . . . . . . . . . 62
Table 55. SnPb eutectic process (from J-STD-020C) . . . 67
Table 56. Lead-free process (from J-STD-020C) . . . . . . 67
Table 57. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 58. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 70
ULPI HS USB host and peripheral transceiver
C = 12h) bit allocation . . . . . . . . . . . . . . . . . . . 48
(address R = 10h to 12h, W = 10h, S = 11h,
C = 12h) bit description . . . . . . . . . . . . . . . . . . 48
(address R = 13h) bit allocation . . . . . . . . . . . 48
(address R = 13h) bit description . . . . . . . . . . 49
(address R = 14h) bit allocation . . . . . . . . . . . 49
(address R = 14h) bit description . . . . . . . . . . 49
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 49
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 50
W = 16h, S = 17h, C = 18h) bit description . . . 50
(address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh,
C = 3Fh) bit allocation . . . . . . . . . . . . . . . . . . . 50
(address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh,
C = 3Fh) bit description . . . . . . . . . . . . . . . . . . 51
(CLOCK, DIR, STP, NXT, DATA[7:0],
RESET_N/PSW_N) . . . . . . . . . . . . . . . . . . . . . 54
(DP, DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
(DP, DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
ISP1505A; ISP1505C
BUS
BUS
BUS
comparators . . . . 57
resistors . . . . . . . . 57
© NXP B.V. 2008. All rights reserved.
/FAULT . . . . . . 55
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