ISP1505CBSGE ST-Ericsson Inc, ISP1505CBSGE Datasheet - Page 19

• Manufacturer Part Number: ISP1505CBSGE
• Description: IC ULPI TRANSCEIVER 24-HVQFN
• Manufacturer: ST-Ericsson Inc
• Type: Transceiverr

Specifications of ISP1505CBSGE

• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 4.5 V
• Mounting Type: Surface Mount
• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• For Use With: ISP1505CBS T&MT KIT - EVAL KIT FOR ISP1505 IC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Other names: ISP1505CBS; ISP1505CBS

NXP Semiconductors
9. Protocol description
ISP1505A_ISP1505C_3
Product data sheet
9.1 ULPI references
9.2 Power-On Reset (POR)
9.3 Power-up, reset and bus idle sequence
The following subsections describe the protocol for using the ISP1505.
The ISP1505 provides a 12-pin ULPI interface to communicate with the link. It is highly
recommended that you read UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 and
UTMI+ Specification Rev. 1.0 .
An internal POR is generated when REG1V8 rises above V
t
below V
voltage on REG1V8 is generated from V
To give a better view of the functionality,
internal POR starts with logic 0 at t0. At t1, the detector will see the passing of the trip
level so that POR turns to logic 1 and a delay element will add another t
drops to logic 0. If REG1V8 dips from t2 to t3 for > t
generated. If the dip at t4 to t5 is too short, that is, < t
will not react and will remain LOW.
Figure 4
On power-up, the ISP1505 performs an internal power-on reset and asserts DIR to
indicate to the link that the ULPI bus cannot be used. When the internal PLL is stable, the
ISP1505 deasserts DIR. The power-up time depends on the V
crystal start-up time, and PLL start-up time t
the ISP1505 drives the NXT pin to LOW and drives DATA[7:0] with RXCMD values. When
DIR is deasserted, the link must drive the data bus to a valid level. By default, the link
must drive data to LOW. When the ISP1505 initially deasserts DIR on power-up, the link
must ignore all RXCMDs until it resets the ISP1505. Before beginning USB packets, the
link must set the RESET bit in the Function Control register to reset the ISP1505. After the
RESET bit is set, the ISP1505 will assert DIR until the internal reset completes. The
ISP1505 will automatically deassert DIR and clear the RESET bit when reset has
completed. After every reset, an RXCMD is sent to the link to update USB status
information. After this sequence, the ULPI bus is ready for use and the link can start USB
operations.
w(REG1V8_H)
Fig 3.
POR(trip)
shows a typical start-up sequence.
Internal power-on reset timing
t0
. The internal POR pulse will also be generated whenever REG1V8 drops
for more than t
t1
t
PORP
Rev. 03 — 26 August 2008
w(REG1V8_L)
t2
Figure 3
CC
ULPI HS USB host and peripheral transceiver
, and then rises above V
.
startup(o)(CLOCK)
ISP1505A; ISP1505C
t3
t
PORP
shows a possible curve of REG1V8. The
w(REG1V8_L)
w(REG1V8_L)
t4
. Whenever DIR is asserted,
POR(trip)
t5
CC
, another POR pulse is
, the internal POR pulse
supply rise time, the
POR(trip)
, for at least
© NXP B.V. 2008. All rights reserved.
004aaa751
PORP
REG1V8
V
POR
POR(trip)
again. The
before it
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